I am looking for an articles and or data of how the substrate noise
of a chip influence the input buffers' trip-point levels. Assuming the substrate
of the chip, connected directly to the leadframe, is noisy and the input buffer
is conencted to other power supply, much smaller ripple on it, how does this
noise (coupled to the core chip) influence th elevels into which the input
buffer will toggele..?
regards, yehuda
-- ------------------------------------------------------------------- Yehuda D. YizraeliZoran Microelectronics Ltd. E-mail: [email protected] Advanced Technology Center Direct Tel: 972-4-85-45-795 P.O.B. 2495, Haifa 31204, Israel Operator : 972-4-85-45-777 http://www.zoran.com Fax : 972-4-8-551-550 -------------------------------------------------------------------
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