RE: [SI-LIST] : Excessive clock overshoot

Charles Hill (chuckh@csn.net)
Fri, 15 May 1998 00:28:32 -0600

Fabrizio,

The drive level is very high in FCT drivers, especially on the negative
edge because the outputs are BiCMOS (that is, have both MOS and bipolar
transistors) that drive the logic levels. This stuff is designed to be
fast, and it is.

As Andrew Ingraham stated:
>I expect that it is the load, but it could be the source package too, or
>both.

>Your terminations don't match the main bus's impedance, so there will be
>reflections; and when there are reflections back and forth, there are
>resonances. I think D. C. Sessions hinted the same.

This is also true. It is an interesting excercise to derive the Laplace
transfer function for the system. What you find is an ugly transfer
function with a transcendental function describing the pole positions.
Doing an inverse transform brings out the following characteristics of the
system:
1. Increasing source inductance increases ringing amplitude at the
receiver.
2. Decreasing load capacitance increases ringing amplitude at the
receiver.
3. Faster slew rates at the driver increases ringing amplitude at the
receiver.
4. Increasing source resistance decreases ringing amplitude at the
receiver.

Looking at the pole positions of the transfer function shows multiple poles
which would be at 1/4, 3/4, 5/4 wavelength and so on if the load
capacitance and source inductance were zero, but the pole positions
decrease in frequency as the load capacitance increases, or the source
inductance increases. This circuit configuration is a capacitively and
inductively loaded transmission line stub.

Describing this "beast" in terms of reflections is an incomplete
description of the system. Now lets think in the frequency domain. At
sufficiently low frequencies, the transit time (the time it takes a signal
to go from source to load and back to source again) is small compared to
the period. The reflection view works when the transit time is significant
with respect to the period of the driving signal. And now back to the time
domain; but a transient waveform like a digital edge has frequency
components throughout the spectrum. So thinking in terms of "reflections"
sometimes works, and sometimes not. Nature does not prescribe a boundary
where the models switch from looking at the line as an LCR network (low
frequency) to a distributed network (high frequency, reflections); both are
valid. Note a line terminated in the characteristic impedance at low
frequency can be viewed as an LCR network with a Q of 1! If you want to
test the reflection argument, try to figure out how the ringing frequency
relates to the transit time of the cable, with the capacitive and inductive
loading present (of course). The poles of the transfer function describes
it quite well.

It seems you are describing a system where there are no clamping diodes to
VCC at the receiving end. But even when the clamping diodes are present,
the ringing energy is still present even though the voltage is limited (the
current is still there). I have seen this be so bad with FCT logic driving
that on HL edges, some devices such as PALs become non functional for a
short period of time due to the forward biasing of the PAL substrate
junction (all the devices in the chip sit on PN junctions to substrate
which must be reverse biased). A careful choice of devices on the
backplane is a good idea.

Arpad asserts n-channel pullups at the source as the cause--this may or may
not be true. I have used drivers of this type and seen no effects of
increasing ringing amplitude at the load due to the driver type. The
reflection argument may not hold in this case and the LCR network may be
closer to the real case. Using that LCR model, when the DC level goes
higher than 3.5 to 4.0 volts (due to a reversal of current direction) the
FCT output impedance goes capacitive, and the circuit resonances simply
change--energy accumulates on that capacitance. But check the ringing
frequency to see if the reflections (transit time) or LCR model applies (1
/ 4.4ns = 227MHz which does not equal 45MHz). Remember, a capacitive load
on the transmission line does not change the transit time on the line, and
the magnitude of the reflection coefficient of a capacitive load is 1.

Also, you mention no undershoot. I would expect the low side clamp diodes
to be turned on when you have 7 volts of overshoot.

So there are several possibilities here (most mentioned previously).
Adding clamp diodes (using some kind of CMOS) to the inputs of your
daughter boards will create problems if you use multiple power supplies.

I hope this makes the situation a little clearer (although it is really
kind of complex). My choice is 74ABT drivers.

Charles Hill, consultant
chuckh@altaeng.com

----------
From: Muranyi, Arpad[SMTP:arpad.muranyi@intel.com]
Sent: Thursday, May 14, 1998 9:13 AM
To: "si-list@silab.Eng.Sun.COM" ;
"'fabrizio=zanella%eng%emchop1@fishbowl02.lss.emc.com'" ; "Charles Hill"
Subject: RE: [SI-LIST] : Excessive clock overshoot

Fabrizio,

Even though Charles is correct, the problem is not so much the high speed
and/or
stength, in my opinion. If I remember correctly, these devices use
n-channel
pullups which have a very high impedance above a transistor threshold
voltage
below the high rail (~3.5-4.0 volts for a 5 volt device). This high
impedance
and the lack of clamping diodes (or clamping circuits) results in an open
ended
transmission line, which allows the reflections to double the amplitude.

Use fast and strong devices if you need the speed, but make sure your lines
are
properly terminated (clamped).

Arpad
========================================================================
====
====

Fabrizio,

I have seen this many times before with FCT logic. In my experience it is
the worst choice of logic families from a signal integrity point of view.
The edge speed is very fast, and current drive is very high, and so the
speed is fast---but that is bad for signal integrity. I suggest you try
ABT, or F. There is also other types of FCT which are intended to be more
"SI friendly".

Charles Hill, consultant
chuckh@altaeng.com

----------
From: fabrizio
zanella[SMTP:fabrizio=zanella%eng%emchop1@fishbowl02.lss.emc.com]
Reply To: fabrizio=zanella%eng%emchop1@fishbowl02.lss.emc.com
Sent: Wednesday, May 13, 1998 2:16 PM
To: si-list@silab.Eng.Sun.COM
Subject: [SI-LIST] : Excessive clock overshoot

I have a question regarding an FCT clock (TTL levels) driving a heavily
loaded backplane. On the driver pin we see excessive overshoot on the L-H
transition which increases as we increase the clock frequency. This
overshoot goes from 5V at 33MHz to 6.5-7.0V at 45MHz. The stub impedance
is 75 ohms, backplane impedance 25 ohms loaded. There is a clamping diode
on the H-L side but not on the L-H. The H-L side does not have any
undershoot.
I have asked the manufacturer and they have never seen this phenomena, nor
do they have an explanation for it.
Any ideas on what could be causing this?

thanks and regards,
Fabrizio Zanella
Design Engineer
EMC Corporation
508-435-1000
fzanella@emc.com