[SI-LIST] : Differential Clock Signal Pair

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From: Brian Seol (BSeol@tessera.com)
Date: Mon May 15 2000 - 09:37:45 PDT


Hi everyone,

I have a simple question about trace layout design for a differential clock
signal pair of high-speed CMOS memory packages. I have two design
guidelines for that as follows:

1. SPACING between a differential clock signal trace pair must be
    MINIMIZED as well as matched in length in order to reduce noise.

2. Differential clock signal trace pair must be matched in length in order
    to achieve matched electrical characteristics, but SPACING between
    them must be MAXIMIZED in order to reduce crosstalk noise.

Which do you prefer?

Thanks and regards,

Brian

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