From: Brian Seol (BSeol@tessera.com)
Date: Mon May 15 2000 - 09:37:45 PDT
I have a simple question about trace layout design for a differential clock
signal pair of high-speed CMOS memory packages. I have two design
guidelines for that as follows:
1. SPACING between a differential clock signal trace pair must be
MINIMIZED as well as matched in length in order to reduce noise.
2. Differential clock signal trace pair must be matched in length in order
to achieve matched electrical characteristics, but SPACING between
them must be MAXIMIZED in order to reduce crosstalk noise.
Which do you prefer?
Thanks and regards,
**** To unsubscribe from si-list or si-list-digest: send e-mail to
firstname.lastname@example.org. In the BODY of message put: UNSUBSCRIBE
si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu
This archive was generated by hypermail 2b29 : Wed Nov 22 2000 - 10:50:19 PST