RE: [SI-LIST] : Differential Clock Signal Pair

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From: Degerstrom, Michael J. (degerstrom.michael@mayo.edu)
Date: Fri May 19 2000 - 13:31:31 PDT


Lee,

Why would the "crosstalk coupling" between the true and complement
pair of a differential pair give worsen your signal integrity?
I think what was implied was that the odd-mode impedance would
match your choice of termination. Could your odd-mode be traveling
in a much more lossy material? Even so, as a practical manner,
it is difficult to get strong odd-mode coupling on a pcb unless
you resort to broadside coupling.

Mike

_______________________________________________________________

> -----Original Message-----
> From: Ritchey Lee [mailto:leeritchey@earthlink.net]
> Sent: Friday, May 19, 2000 11:54 AM
> To: si-list@silab.eng.sun.com
> Subject: Re: [SI-LIST] : Differential Clock Signal Pair
>
>
> When the data rate gets very fast, ala 2.5 GB/s, this
> "crosstalk coupling" has
> an errosive effect on edge rate and jitter. In such cases we
> spread the signals
> out so there is little or no coupling. It probably has some
> errosive effect at
> slower data rates as well, but there is more timng margin, so
> less worry.
>
> Lee
>
> Doug Brooks wrote:
>
> > Differential signals are a special case of crosstalk
> coupling where the
> > correlation between the signals is (a) known and (b)
> perfectly correlated
> > with each other with (c) a correlation coefficient of -1.
> In this special
> > case, you WANT the crosstalk coupling --- it works in your
> favor. So you
> > want the traces to be as close as possible (practical).
> >
> > To see some of the mathematics of why, see the article "Impedance
> > Terminations, What's the Value" on our web site at
> > http://www.ultracad.com
> >
> > Doug Brooks
> >
> > At 09:37 AM 5/15/00 -0700, you wrote:
> > >Hi everyone,
> > >
> > >I have a simple question about trace layout design for a
> differential clock
> > >signal pair of high-speed CMOS memory packages. I have two design
> > >guidelines for that as follows:
> > >
> > >1. SPACING between a differential clock signal trace pair must be
> > > MINIMIZED as well as matched in length in order to
> reduce noise.
> > >
> > >2. Differential clock signal trace pair must be matched in
> length in order
> > > to achieve matched electrical characteristics, but
> SPACING between
> > > them must be MAXIMIZED in order to reduce crosstalk noise.
> > >
> > >Which do you prefer?
> > >
> > >Thanks and regards,
> > >
> > >Brian
> >
> > .
> > ************************************************************
> > Doug Brooks' book "Electrical Engineering for the Non-Degreed
> > Engineer" is now available. See our web site for details.
> > .
> > Doug Brooks, President doug@eskimo.com
> > UltraCAD Design, Inc. http://www.ultracad.com
> >
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