RE: [SI-LIST] : Differential Clock Signal Pair

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From: Dave Hoover (dave_hoover@yahoo.com)
Date: Fri May 19 2000 - 17:18:27 PDT


With respect to Broadside Coupled Differential lines;
(From a PCB fabrication stand point) The PCB structure
has more tolerance build up potential.
i.e., with .005" linewidths

--------------------------P
                    Bonding Sheets (Prepreg)

-------|==========|-------S
////////////////////////// Doublesided FR-4 Core
-------|==========|-------S

                    Bonding Sheets (Prepreg)
--------------------------P

The above would be an "ideal" situation.
1)Signals are on an FR-4 Core.
2)Signals are relatively well registered to each
other.
3)Signals are closely coupled.

--------------------------P
                    Bonding Sheets (Prepreg)

--|==========|------------S
////////////////////////// Doublesided FR-4 Core
-------|==========|-------S

                    Bonding Sheets (Prepreg)
--------------------------P

The above is a more "realistic" situation.
We have some front-to-back misregistration (1 set)
but it is well within the PCB overall stack-up
tolerances. A fabricator can hold hold front-to-back
fairly well. Now if the FR-4 core HAD to be the plane
to signal dielectrics (due to stack-up requirements),
then we would be dealing with two sets of tolerances
that could be cumulative. The results would be fairly
gross. Especially for relatively small linewidths.

Edge Coupled Differential does not have this issue.

When specifying Broadside Coupled Differential, in
order to keep the tolerances down to one set, make
sure the stack-up ends up with that signal pair on an
FR-4 core. There seems to be more and more demand for
BS Coupled Differential lines. This appears to be
driven by 2.0mm connectors (staggered). Seems that for
differential pairs there is no other way to rout out
from that connector. : /

Dave Hoover

--- "Moran, Brian P" <brian.p.moran@intel.com> wrote:
> As I mentioned way back at the beginning of this
> dialoque I believe
> broadside coupled differential pairs are also a good
> solution for some
> applications. In particular where length tuning is
> important such as with
> very high frequency clocks and/or 2 GHz and above
> parallel interfaces. This
> eliminates length matching problems and excessive
> vias problems, and
> provides better characteristics overall. The
> problem is it is difficult to
> acheive high differential impedances.
>
> Brian P. Moran
> Intel Corporation, FM6-45
> 1900 Praire City Road
> Folsom, CA 95630
> brian.p.moran@intel.com
> (916) 356-1912
>
>
> -----Original Message-----
> From: Ritchey Lee [mailto:leeritchey@earthlink.net]
> Sent: Friday, May 19, 2000 9:54 AM
> To: si-list@silab.eng.sun.com
> Subject: Re: [SI-LIST] : Differential Clock Signal
> Pair
>
>
> When the data rate gets very fast, ala 2.5 GB/s,
> this "crosstalk coupling"
> has
> an errosive effect on edge rate and jitter. In such
> cases we spread the
> signals
> out so there is little or no coupling. It probably
> has some errosive effect
> at
> slower data rates as well, but there is more timng
> margin, so less worry.
>
> Lee
>
> Doug Brooks wrote:
>
> > Differential signals are a special case of
> crosstalk coupling where the
> > correlation between the signals is (a) known and
> (b) perfectly correlated
> > with each other with (c) a correlation
> coefficient of -1. In this
> special
> > case, you WANT the crosstalk coupling --- it works
> in your favor. So you
> > want the traces to be as close as possible
> (practical).
> >
> > To see some of the mathematics of why, see the
> article "Impedance
> > Terminations, What's the Value" on our web site at
> > http://www.ultracad.com
> >
> > Doug Brooks
> >
> > At 09:37 AM 5/15/00 -0700, you wrote:
> > >Hi everyone,
> > >
> > >I have a simple question about trace layout
> design for a differential
> clock
> > >signal pair of high-speed CMOS memory packages.
> I have two design
> > >guidelines for that as follows:
> > >
> > >1. SPACING between a differential clock signal
> trace pair must be
> > > MINIMIZED as well as matched in length in
> order to reduce noise.
> > >
> > >2. Differential clock signal trace pair must be
> matched in length in
> order
> > > to achieve matched electrical
> characteristics, but SPACING between
> > > them must be MAXIMIZED in order to reduce
> crosstalk noise.
> > >
> > >Which do you prefer?
> > >
> > >Thanks and regards,
> > >
> > >Brian
> >
> > .
> >
>
************************************************************
> > Doug Brooks' book "Electrical Engineering for the
> Non-Degreed
> > Engineer" is now available. See our web site for
> details.
> > .
> > Doug Brooks, President
> doug@eskimo.com
> > UltraCAD Design, Inc.
> http://www.ultracad.com
> >
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