RE: [SI-LIST] : Differential Clock Signal Pair

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From: Degerstrom, Michael J. (degerstrom.michael@mayo.edu)
Date: Wed May 17 2000 - 13:28:03 PDT


Brian,

After reading the responses to your posting I think Scott
gave the most concise answer. Just keep in mind that as you
tightly couple the true and complement lines together (by
minimizing the spacing between the t/c pair) then your
characteristic impedance will shift downward unless you
narrow your lines to compensate.

Mike

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Mike Degerstrom Email: degerstrom.michael@mayo.edu
Mayo Clinic
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> -----Original Message-----
> From: Scott McMorrow [mailto:scott@vasthorizons.com]
> Sent: Monday, May 15, 2000 2:53 PM
> To: si-list@silab.eng.sun.com
> Subject: Re: [SI-LIST] : Differential Clock Signal Pair
>
>
> Brian,
>
> I believe 1) refers to the track to track spacing of the positive and
> negative sides of the differential pair.
>
> I believe 2) refers to the side to side spacing of two different
> differential pairs.
>
> regards,
>
> scott
>
> --
> Scott McMorrow
> Principal Engineer
> SiQual, Signal Quality Engineering
> 18735 SW Boones Ferry Road
> Tualatin, OR 97062-3090
> (503) 885-1231
> http://www.siqual.com
>
>
> Brian Seol wrote:
>
> > Hi everyone,
> >
> > I have a simple question about trace layout design for a
> differential clock
> > signal pair of high-speed CMOS memory packages. I have two design
> > guidelines for that as follows:
> >
> > 1. SPACING between a differential clock signal trace pair must be
> > MINIMIZED as well as matched in length in order to reduce noise.
> >
> > 2. Differential clock signal trace pair must be matched in
> length in order
> > to achieve matched electrical characteristics, but
> SPACING between
> > them must be MAXIMIZED in order to reduce crosstalk noise.
> >
> > Which do you prefer?
> >
> > Thanks and regards,
> >
> > Brian
> >
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