Re: [SI-LIST] : Differential Clock Signal Pair

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From: Scott McMorrow (scott@vasthorizons.com)
Date: Mon May 15 2000 - 12:53:03 PDT


Brian,

I believe 1) refers to the track to track spacing of the positive and
negative sides of the differential pair.

I believe 2) refers to the side to side spacing of two different
differential pairs.

regards,

scott

--
Scott McMorrow
Principal Engineer
SiQual, Signal Quality Engineering
18735 SW Boones Ferry Road
Tualatin, OR  97062-3090
(503) 885-1231
http://www.siqual.com

Brian Seol wrote:

> Hi everyone, > > I have a simple question about trace layout design for a differential clock > signal pair of high-speed CMOS memory packages. I have two design > guidelines for that as follows: > > 1. SPACING between a differential clock signal trace pair must be > MINIMIZED as well as matched in length in order to reduce noise. > > 2. Differential clock signal trace pair must be matched in length in order > to achieve matched electrical characteristics, but SPACING between > them must be MAXIMIZED in order to reduce crosstalk noise. > > Which do you prefer? > > Thanks and regards, > > Brian > > **** To unsubscribe from si-list or si-list-digest: send e-mail to > majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE > si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP. > si-list archives are accessible at http://www.qsl.net/wb6tpu > ****

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