Re: [SI-LIST] : Differential Clock Signal Pair

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From: Neven Pischl (npischl@cisco.com)
Date: Mon May 15 2000 - 14:44:36 PDT


The spacing between the traces of the pair AND anything else should be maximized, but not between the traces in the pair.

Neven

At 09:37 AM 5/15/00 -0700, you wrote:
>Hi everyone,
>
>I have a simple question about trace layout design for a differential clock
>signal pair of high-speed CMOS memory packages. I have two design
>guidelines for that as follows:
>
>1. SPACING between a differential clock signal trace pair must be
> MINIMIZED as well as matched in length in order to reduce noise.
>
>2. Differential clock signal trace pair must be matched in length in order
> to achieve matched electrical characteristics, but SPACING between
> them must be MAXIMIZED in order to reduce crosstalk noise.
>
>Which do you prefer?
>
>Thanks and regards,
>
>Brian
>
>
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