RE: [SI-LIST] : Differential Clock Signal Pair

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From: Dunbar, Tony (Tony_Dunbar@mentorg.com)
Date: Mon May 15 2000 - 12:55:20 PDT


Brian,

Number 1 every time, but the spacing between the pair traces cannot simply
be minimized without attention to the differential impedance. The preferred
approach I would put forward is aim to use a separation equal to your
manufacturing rule for trace-trace separation (which kindof minimizes the
spacing) and then alter the trace widths to obtain the differential
impedance best suited to your application.

As regards number 2, I would check the source of that guideline very
carefully and make sure something hasn't got scrambled. The only crosstalk
that is reduced is that which would be, for the most part, common to both
traces in the pair. This approach would tend to MAXIMIZE non-common
crosstalk and lead to line mis-match problems such as timing imbalance -
just like not matching the lengths of each trace.

Regards,
Tony

-----Original Message-----
From: Brian Seol [mailto:BSeol@tessera.com]
Sent: Monday, May 15, 2000 11:38 AM
To: si-list@silab.eng.sun.com
Subject: [SI-LIST] : Differential Clock Signal Pair

Hi everyone,

I have a simple question about trace layout design for a differential clock
signal pair of high-speed CMOS memory packages. I have two design
guidelines for that as follows:

1. SPACING between a differential clock signal trace pair must be
    MINIMIZED as well as matched in length in order to reduce noise.

2. Differential clock signal trace pair must be matched in length in order
    to achieve matched electrical characteristics, but SPACING between
    them must be MAXIMIZED in order to reduce crosstalk noise.

Which do you prefer?

Thanks and regards,

Brian

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