From: Peterson, James F (FL51) (email@example.com)
Date: Tue Aug 29 2000 - 09:59:58 PDT
Here's my hold time dilemma/question :
I have a synchronous ram with a tco (clk to valid out) of (1ns,3ns). I have
a processor with a tHold of 1ns (min). Taking the min. tco for a hold time
analysis gives me 0ns of margin. Any clock skew at all between the ram and
the processor makes this fail timing analysis.
It used to be that one solution was to invert the clock to the ram, but
these days it's hard to justify cutting the board's settling time by 50% (At
100MHz, you've gone from a starting budget of 10ns to one of 5ns).
What are some you high speed board designers doing about this?
(BTW : This reminds me of a story : about 6 years ago I purchased a
computer. I noticed that the machine locked up every once in a while. At
first I thought it was the typical OS problems we all encounter, but it was
occurring so frequently I called the supplier. They responded that my case
was a known problem with that mother board and the fix was to go into the
bios and disable the external synchronous L2 cache!!!!)
> Jim Peterson
> Honeywell Space Systems
> M/S 934-5
> 13350 U.S. Hwy 19 N.
> Clearwater FL, 33764-7290
> Office : 727-539-2719
> Fax : 727-539-2183
**** To unsubscribe from si-list or si-list-digest: send e-mail to
firstname.lastname@example.org. In the BODY of message put: UNSUBSCRIBE
si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu
This archive was generated by hypermail 2b29 : Tue May 08 2001 - 14:29:22 PDT