Re: [SI-LIST] : hold time dilemma

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From: Bob Perlman (bobperl@best.com)
Date: Tue Aug 29 2000 - 11:09:53 PDT


Jim -

What do do about hold time? Let me count the ways:

1) Delay the clock to the synchronous SRAM. The catch, of
course, is that now you may introduce an address or data hold
time problem for writes to the SRAM.

2) Create a data path delay by adding trace length to the data
lines. It's ugly and hogs routing (you'll need 6" per ns), and a trace
of any appreciable length will need termination, perhaps on both
ends. And the extra delay will erode your data setup margin.

3) Add a (bidirectional) data latch between processor and RAM,
and gate open a latch with a B-phase clock, i.e., a clock that goes
HIGH 1/4 cycle after the SRAM/processor clock. Of course, you
have to generate such a clock, and also have to generate direction
enables for the latch outputs. Alternately, just introduce a
bidirectional buffer with a min delay of a ns or so. In either case,
setup margins are degraded, perhaps fatally.

4) See if the SRAM vendor(s) is willing to sign up for a longer
minimum output data hold time. Then create a special source
control drawing--a data sheet, in effect--that documents the
increased hold time; have the vendor sign it. This is dangerous,
because there's no telling how conscientious the company will be
in meeting this new spec. You could use the signed spec to get
them to refund what you paid for non-compliant parts, but that
doesn't help when you're trying to ship a system. You could also
look for another SRAM vendor whose minimum data CP->Q delays
are longer, but that'll reduce the number of vendors.

5) My last suggestion is going to seem woefully impractical, but
here it is. Don't use processors that have positive hold times on
the data bus; as you've discovered, they make design extremely
difficult. Selection of processors and other parts should include, at
a very early stage, a thorough review of AC specs. Eliminating
processors on this basis may seem excessively restrictive, until
you consider the difficulty of actually solving the resulting hold time
problems if you don't. If you do reject parts that have positive hold
times, MAKE SURE THE VENDOR KNOWS! I have a theory that
semiconductor companies periodically round up all of the IC
designers who understand I/O setup/hold time issues and shoot
them. These companies need constant reminders that such
issues are important.

This is a difficult issue, and the difficulty is one of the reasons that
lots of designers ignore potential hold time problems. I can't
recommend doing that, though.

Good luck,
Bob Perlman

> Here's my hold time dilemma/question :
>
> I have a synchronous ram with a tco (clk to valid out) of (1ns,3ns). I
> have a processor with a tHold of 1ns (min). Taking the min. tco for a
> hold time analysis gives me 0ns of margin. Any clock skew at all
> between the ram and the processor makes this fail timing analysis.
>
> It used to be that one solution was to invert the clock to the ram,
> but these days it's hard to justify cutting the board's settling time
> by 50% (At 100MHz, you've gone from a starting budget of 10ns to one
> of 5ns).
>
> What are some you high speed board designers doing about this?
>
> (BTW : This reminds me of a story : about 6 years ago I purchased a
> computer. I noticed that the machine locked up every once in a while.
> At first I thought it was the typical OS problems we all encounter,
> but it was occurring so frequently I called the supplier. They
> responded that my case was a known problem with that mother board and
> the fix was to go into the bios and disable the external synchronous
> L2 cache!!!!)
>
> best regards,
>
> Jim
>
> > Jim Peterson
> > james.f.peterson@honeywell.com
> > Honeywell Space Systems
> > M/S 934-5
> > 13350 U.S. Hwy 19 N.
> > Clearwater FL, 33764-7290
> > Office : 727-539-2719
> > Fax : 727-539-2183
> >
>
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>

===========
Bob Perlman
Cambrian Design Works
Digital design and signal integrity consulting
http://www.cambriandesign.com

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