RE: [SI-LIST] : hold time dilemma

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From: Chris Hansen (chris.hansen@storlogic.com)
Date: Tue Aug 29 2000 - 10:52:56 PDT


I had this exact situation in a design. If you do as you suggest, and try
to center sample by inverting the clock to the SDRAM, you may be moving your
problem from a hold time violation to a setup time violation. Here is what
I suggest, and here is a situation where some trace length will actually
help. Take your clock through a zero skew buffer. I think that Cypress
Semiconductor makes a couple of 1 in, multiple out devices (PLL based) that
will fit the bill. From each output of the zero skew buffer, route
point-to-point to each of the SDRAM devices and to the processor. Match the
length of these clock routes exactly ... not only the overall lengths, but
also the layer transitions as well. This will give you a very minimal
amount of skew between the clocks to all of the devices. Now when routing
the address and data lines between the SDRAMs and the processor, maximize
this length, but not too long to ruin your signal integrity, and this will
give you your timing margin (Ttrace prop delay - T clock skew) for the hold
time. Hopefully, and in the case of my design it did not, this will not
create a setup time violation.

Chris Hansen
Director of Hardware Development

StorLogic
100 Technology Park, Suite 175
Lake Mary, Florida 32746-6926
Tel: (407) 333 9998 x242
Fax: (407) 333 4448

mailto:chris.hansen@storlogic.com
www.storlogic.com

-----Original Message-----
From: Peterson, James F (FL51) [mailto:james.f.peterson@honeywell.com]
Sent: Tuesday, August 29, 2000 1:00 PM
To: si-list@silab.eng.sun.com
Subject: [SI-LIST] : hold time dilemma

Here's my hold time dilemma/question :

I have a synchronous ram with a tco (clk to valid out) of (1ns,3ns). I have
a processor with a tHold of 1ns (min). Taking the min. tco for a hold time
analysis gives me 0ns of margin. Any clock skew at all between the ram and
the processor makes this fail timing analysis.

It used to be that one solution was to invert the clock to the ram, but
these days it's hard to justify cutting the board's settling time by 50% (At
100MHz, you've gone from a starting budget of 10ns to one of 5ns).

What are some you high speed board designers doing about this?

(BTW : This reminds me of a story : about 6 years ago I purchased a
computer. I noticed that the machine locked up every once in a while. At
first I thought it was the typical OS problems we all encounter, but it was
occurring so frequently I called the supplier. They responded that my case
was a known problem with that mother board and the fix was to go into the
bios and disable the external synchronous L2 cache!!!!)

best regards,

Jim

> Jim Peterson
> james.f.peterson@honeywell.com
> Honeywell Space Systems
> M/S 934-5
> 13350 U.S. Hwy 19 N.
> Clearwater FL, 33764-7290
> Office : 727-539-2719
> Fax : 727-539-2183
>

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