From: Ingraham, Andrew (Andrew.Ingraham@compaq.com)
Date: Tue Aug 29 2000 - 10:17:16 PDT
> I have a synchronous ram with a tco (clk to valid out) of (1ns,3ns). I
> a processor with a tHold of 1ns (min). Taking the min. tco for a hold time
> analysis gives me 0ns of margin. Any clock skew at all between the ram and
> the processor makes this fail timing analysis.
Try delaying the clock to the SRAM by a nanosecond or so; it's less severe
than the 5+ ns equivalent delay of inverting the clock.
**** To unsubscribe from si-list or si-list-digest: send e-mail to
email@example.com. In the BODY of message put: UNSUBSCRIBE
si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu
This archive was generated by hypermail 2b29 : Tue May 08 2001 - 14:29:22 PDT