Re: [SI-LIST] : Copper balance

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From: Dave Hoover (dave_hoover@yahoo.com)
Date: Sun Feb 11 2001 - 00:42:05 PST


Dorin,
(From a Fabrication Stand Point)
My experience is more around something I've heard
called the "antennae effect" where the floating
(isolated) copper will be capacitive and couple with
any signals close by. So many fabricators tend to
break the copper thieving up into small isolated
features. (circles or squares) A couple of important
things to comment on would be to maintain the
isolation of these features away from other traces or
pads. (20H Rule) And to make sure that when the
fabricator generates the thieving that they also
include ALL signals contained within each reference
plane group. (i.e., a dualstripline would need both
signals (temporarily) merged to generate the pattern.
Or if layers 1 and two were signals, they would also
need to be merged to generate the thieving or else the
squares might end up being rignt on top of a signal
trace.)

Dave Hoover - Director of Technology

--- DORIN OPREA <dorin.oprea@alcatel.com> wrote:
> Thanks Chris. The main problem is the PCB vendor
> wanted to have 40% copper
> convereage on the layer and this implies small
> spacing between the floating copper
> geometries. Having squares 5x5 mm with the spacing
> 10 mm will give < 25% copper
> coverage; therefore less spacing is required. But
> what is the smallest spacing and
> what is the copper geometry to get 40% ?
>
> Dorin
>
>
>
> Chris Padilla wrote:
>
> > It is called thieving and I've found so signifcant
> EMI results positive or
> > negative as a result. Just set a spacing criteria
> from any components like
> > "no closer than 500 mils to any componenet or
> trace or via or whatever."
> >
> > If the board has lots of blank space to fill, the
> EMI team may wish to
> > consider making embedded caps with the free space
> and copper flood
> > depending on the reference plane nearby. I have
> found these caps to be of
> > significant importance in controlling emissions
> and they are basically "free!"
> >
> > Good Luck----->Chris
> >
> > >Hi,
> > >
> > >I am working now on the copper balance issue we
> have on our PCBs. On the
> > >outer layer beneath the converter a copper
> surface is required (E
> > >shielding) which generates the copper balance
> issue on that particular
> > >layer and also throughout the stack up. Thus, the
> unpopulated copper
> > >space is filled with square or circle floating
> copper surfaces separated
> > >in-between. These squares are overlapping
> throughout the stack up. The
> > >question: what is the best copper geometry, its
> dimension and the
> > >spacing between these geometries ?. Copper
> balance requires as much
> > >copper as possible but EMC wants no floating
> copper and very weak
> > >coupling between noisy areas such as converter
> and any functional
> > >digital area.
> > >
> > >Your help is really appreciated,
> > >Dorin
> > >
> > >
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