Re: [SI-LIST] : Copper balance

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From: DORIN OPREA (dorin.oprea@alcatel.com)
Date: Wed Jan 10 2001 - 11:55:58 PST


Thanks Chris. The main problem is the PCB vendor wanted to have 40% copper
convereage on the layer and this implies small spacing between the floating copper
geometries. Having squares 5x5 mm with the spacing 10 mm will give < 25% copper
coverage; therefore less spacing is required. But what is the smallest spacing and
what is the copper geometry to get 40% ?

Dorin

Chris Padilla wrote:

> It is called thieving and I've found so signifcant EMI results positive or
> negative as a result. Just set a spacing criteria from any components like
> "no closer than 500 mils to any componenet or trace or via or whatever."
>
> If the board has lots of blank space to fill, the EMI team may wish to
> consider making embedded caps with the free space and copper flood
> depending on the reference plane nearby. I have found these caps to be of
> significant importance in controlling emissions and they are basically "free!"
>
> Good Luck----->Chris
>
> >Hi,
> >
> >I am working now on the copper balance issue we have on our PCBs. On the
> >outer layer beneath the converter a copper surface is required (E
> >shielding) which generates the copper balance issue on that particular
> >layer and also throughout the stack up. Thus, the unpopulated copper
> >space is filled with square or circle floating copper surfaces separated
> >in-between. These squares are overlapping throughout the stack up. The
> >question: what is the best copper geometry, its dimension and the
> >spacing between these geometries ?. Copper balance requires as much
> >copper as possible but EMC wants no floating copper and very weak
> >coupling between noisy areas such as converter and any functional
> >digital area.
> >
> >Your help is really appreciated,
> >Dorin
> >
> >
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