RE: [SI-LIST] : Split ground on top of PCB

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From: JTrammel (jdtramme@bellsouth.net)
Date: Fri Jan 19 2001 - 06:38:10 PST


Hello,

Need a coefficient of thermal expansion for a 32 layer 0.164" standard
material printed circuit board. Can anyone offer assistance for my
situation.

Thanks,
John

-----Original Message-----
From: Dale Jenkins [SMTP:djenkins@amcoas.com]
Sent: Friday, January 19, 2001 8:37 AM
To: si-list@silab.eng.sun.com
Subject: [SI-LIST] : Split ground on top of PCB

Hello,
I would like any and all OPINION on the following PCB topography:

1. 4 layer, FR-4
top = signal, ground fill
inner = signal, ground fill
power = split DC power plane
bottom = signal, ground fill ( mostly ground )
2. RF Receive & Transmit <500MHz + PLL, dual IF conversion

3. We have partitioned off the top ground fill to
isolate each part of the circuit ( RF amp, IF VCO's, PLL, 2nd IF,
Base band ). We also have vias to ground surrounding each section.
The RF amp, VCO's, 1st IF amp, are shielded.

We did #3 to prevent noise from swamping out the RF signal path to
improve RX sensitivity. The noise seems to come from the PLL.

Does this approach make sense or have we missed the boat!

Thanks, Dale

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