RE: [SI-LIST] : SI analysis: IBIS vs. HSpice

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From: Jim_Pankratz@Dell.com
Date: Fri Jan 19 2001 - 06:35:08 PST


Hey Todd,

Good to hear from you!

As we dive into what I suspect might end up being a lively discussion, I'd
like to go one step further than Pat and ask specifically if your asking
about behavioral modeling vs. transistor level modeling. I intentionally
leave the word Spice out, because in reality you can do behavioral modeling
with Spice (we've been doing that for years). Also, I leave out the word
IBIS because IBIS is a data set not a model in and of itself. So, if
someone wanted to do a nasty little bit of perl scripting you could
certainly take an IBIS data set and create a "transistor" model for that
data set (albeit, a pretty crude, simple one).

So, is that the topic your looking to address, transistor level vs.
behavioral modeling?

Regards,

Jim P.

Jim Pankratz
Dell Signal Integrity Group
512.723.5357
jim_pankratz@dell.com

-----Original Message-----
From: Todd Westerhoff [mailto:twester@hhnetwk.com]
Sent: Friday, January 19, 2001 7:14 AM
To: si-list@silab.eng.sun.com
Subject: [SI-LIST] : SI analysis: IBIS vs. HSpice

Hi all,

I'm curious to know who out there is running SI analysis in BOTH HSpice and
IBIS, and what your thoughts and experiences are (good and bad).

I'm most interested in the strategies people use to ensure they're
simulating the same circuit in both simulators, how people produce/validate
models, and how well the two sets of simulation results are expected to
correlate.

Strategies for tool use (i.e. which kind of simulation do you use for which
part of the design cycle) would also be a good topic for discussion.

Comments (both public and private) are both welcome and appreciated.

Todd.

Todd Westerhoff
SI Engineer
Hammerhead Networks
5 Federal Street
Billerica, MA 01821
twester@hhnetwk.com
ph: 978-671-5084

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