From: Beal, Weston ([email protected])
Date: Thu Jan 04 2001 - 11:41:06 PST
D.C.,
You call this Scalable signaling, but it's not clear from your document how
it scales. What if I'm already using 1.8 Volts for my core and I want to
use that same voltage for I/O?
This looks kind of like GTL terminated to 0V with a pullup driver. Can you
make PMOS drivers fast enough for current and future speeds?
I like your idea, and I'd like to see it go forward. Have you made a
virtual prototype?
Later,
Weston
-----Original Message-----
From: D. C. Sessions [mailto:[email protected]]
Sent: Thursday, January 04, 2001 9:24 AM
To: [email protected]
Subject: [SI-LIST] : Comments on proposed standard
A year ago I tried to start a thread on what a clean-sheet-of-paper
signaling standard would look like. Not much response, so I had to
wing it. Due to intense demand for short IC-to-IC connections at
absurd signaling rates, earlier this month I presented a proposed
standard for Scalable Low-Voltage Signaling to JEDEC's JC-16
committee on electrical interfaces.
A copy of the draft is at http://www.primenet.com/~sessions/SLVS-400.pdf
Comments (or at least germane ones) invited.
-- | The race is not always to the swift, nor the battle to the strong. | | Because the slow, feeble old codgers like me cheat. | +--------------- D. C. Sessions <[email protected]> --------------+**** To unsubscribe from si-list or si-list-digest: send e-mail to [email protected]. In the BODY of message put: UNSUBSCRIBE si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu ****
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