RE: [SI-LIST] : Comments on proposed standard

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From: Haller, Robert (rhaller@cereva.com)
Date: Thu Jan 04 2001 - 10:47:17 PST


DC
   I remember that clean-sheet-of-paper thread request but was to
busy to respond. A quick scan of your draft looks interesting.
  For very high-speed signaling rates, I think the way to go is HSTL
(JEDEC #????) with ON-chip Termination. The only problem is getting
the I/O cell designers to put the termination ON chip.
You'll need a few clases of I/O cells; series terminated for unidirectional
networks, shunt termination for Bi-directional, and for goodness sake
require
all connections to be point-to-point. If you want to use really absurd
signaling rates use Source Syncronous, like most high-speed cpu caches.
That will keep the I/O cell designers busy. And of course we all know who
DC Session is :-)

Bob Haller
Cereva Networks
3 Network Drive Marlboro Ma.
rhaller@cereva.com

-----Original Message-----
From: D. C. Sessions [mailto:si-list@lumbercartel.com]
Sent: Thursday, January 04, 2001 12:24 PM
To: si-list@silab.eng.sun.com
Subject: [SI-LIST] : Comments on proposed standard

A year ago I tried to start a thread on what a clean-sheet-of-paper
signaling standard would look like. Not much response, so I had to
wing it. Due to intense demand for short IC-to-IC connections at
absurd signaling rates, earlier this month I presented a proposed
standard for Scalable Low-Voltage Signaling to JEDEC's JC-16
committee on electrical interfaces.

A copy of the draft is at http://www.primenet.com/~sessions/SLVS-400.pdf

Comments (or at least germane ones) invited.

-- 
| The race is not always to the swift, nor the battle to the strong. |
| Because the slow, feeble old codgers like me cheat.                |
+--------------- D. C. Sessions <dcs@lumbercartel.com> --------------+

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