From: D. C. Sessions ([email protected])
Date: Thu Jan 04 2001 - 18:26:20 PST
On Thursday 04 January 2001 12:41, Beal, Weston wrote:
# You call this Scalable signaling, but it's not clear from your document how
# it scales.
Because the signal range doesn't include the positive rail, it interoperates
across several supply generations. SLVS-400 (with a maximum signal
potential of ~500 mV) should be good for at least three more process
generations (120 nm, 100 nm, and 80 nm)
# What if I'm already using 1.8 Volts for my core and I want to
# use that same voltage for I/O?
Go right ahead. That's basically 1.8v CMOS or SSTL-1.8, the former a
JEDEC standard and the latter in the works.
The problem is that at 1.8v you're already tied to an old technology.
I'm currently working on 120 nm CMOS, which can't handle voltages
over 1.2 V without oxide stress degradation. Your 1.8 V CMOS can't
be used with current processes, and the current stuff would require
thick-oxide (usually 3.3 V) transistors to interoperate. 3.3 V transistor
performance sucks bricks at 1.8 V, and is even worse at 1.2.
Nasty choices, those.
# This looks kind of like GTL terminated to 0V with a pullup driver. Can you
# make PMOS drivers fast enough for current and future speeds?
Who said anything about PMOS? Part of the objective is to have the
signal range be well away from the positive core supply, which means
that NMOS pullups actually work better, including their low output
impedance. The driver _is_ required to maintain a near-line-value
output impedance in both low and high states.
# I like your idea, and I'd like to see it go forward. Have you made a
# virtual prototype?
Yup. First-generation design was primarily for static and impedance
matching studies. The current effort is targeted at getting a good
end-to-end architecture for signaling with UIs of 320 ps. Lookin' good,
too, even though we're using an old process for the present.
# -----Original Message-----
# From: D. C. Sessions [mailto:[email protected]]
# Sent: Thursday, January 04, 2001 9:24 AM
# To: [email protected]
# Subject: [SI-LIST] : Comments on proposed standard
# A year ago I tried to start a thread on what a clean-sheet-of-paper
# signaling standard would look like. Not much response, so I had to
# wing it. Due to intense demand for short IC-to-IC connections at
# absurd signaling rates, earlier this month I presented a proposed
# standard for Scalable Low-Voltage Signaling to JEDEC's JC-16
# committee on electrical interfaces.
# A copy of the draft is at http://www.primenet.com/~sessions/SLVS-400.pdf
# Comments (or at least germane ones) invited.
-- | The race is not always to the swift, nor the battle to the strong. | | Because the slow, feeble old codgers like me cheat. | +--------------- D. C. Sessions <[email protected]> --------------+
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