Re: [SI-LIST] : Decoupling capacitors (again!)

About this list Date view Thread view Subject view Author view

From: Ray Anderson (raymonda@ha1mpk-mail.eng.sun.com)
Date: Tue Aug 15 2000 - 09:55:02 PDT


Martin-

A few comments on your inquiry about selecting decaps for your design.

First of all, I'm glad you found our paper useful. There have
been many developments in our methodology since the publication
of our paper.

Originally the target Z was specified as being flat from DC to
some upper frequency. We have come to realize that although that
may be a desirable goal, that in many situation it results in
an unwieldly number of capacitors. We are now of the opinion
that it is desirable to maintain a flat target impedance at
the lower end of the spectrum (DC to about 200 MHz .
Above a couple of hundred MHz the use of discrete decaps to hold
down the impedance becomes increasingly difficult and ineffective.
The use of thin dielectrics (2 mils or less) is by far the most
effective way of dealing with the impedance at high frequencies.

Also, the impedance may be allowed to rise above the nominal 200MHz
corner frequency without too much effect on the SI performance of
the system. At the lower ("SI") frequencies the concept of target
impedance makes sense. AT the higher ("EMI") frequencies, the
meaning of 'target impedance' is a bit more nebulous and work is
currently in progress to quantify the effect of target Z vs radiated
fields.

At frequencies above about 200 MHz judicious selection of decaps
are made to "sit" on top of high impedance resonances at multiples
of the clock and buss frequencies. (1x, 2x, 3x, etc.). At frequencies
between these 'important' frequencies there may be high impedance
spikes in the target Z profile, but these are at don't-care
frequencies and tend not to cause problems. The effect of having
high Z excursions in the target Z at critical frequencies is to
increase EMI radiation at those frequencies.

You mentioned the need for 500-800 decaps. This is indeed the typical
magnitude of the indicated decoupling cap complement indicated if you
try to maintain a flat response on out to 1 GHz. By allowing the
impedance to rise at the high end and intelligent selection of which
high Z responses to suppress the typical numbe of required decaps
in a high perfmance design can be around 200 or so.

In the end you want to keep the impedance profile down below your
calculated target Z from DC to about 200 MHz. Above that use
thin dielectrics to control the amplitude of the plane resonance
impedance peaks and use selected decaps to suppress responses
at troublesome freqs. (the effectiveness of the caps does decrease
at frequencies above 200 MHz, and at very high frequencies they
tend to be very ineffective so you really need to rely on the the
high quality capacitance and low inductance provided by the thin
dielectric planes.)

Ray Anderson
Sun Microsystems

> Date: Tue, 15 Aug 2000 15:49:08 +0100
> From: "Martin J Thompson" <Martin.J.Thompson@trw.com>
> To: "<\"si-list@silab.eng.sun.com\"" <si-list@silab.eng.sun.com>
> Subject: [SI-LIST] : Decoupling capacitors (again!)
> Mime-Version: 1.0
> Content-Transfer-Encoding: quoted-printable
> Content-Disposition: inline
>
> Hi all, this is my first time posting here, although I've been
lurking for a while.
>
> My problem is figuring out the decoupling requirements for this
system:
> FPGA, DSP, 6 SDRAMS, 2 flash, DPRAM, clock frequency is 100MHz.
>
> According to my calculations, my I/O's need to drive a total of about
1.5nF of I/O and trace capacitance.
> To achieve the 0.5ns edges that the FPGA will drive (3.3V supply) it
looks like I need dI=4amps. This is assuming that 50% (is this
typical?) of the I/O's toggle each cycle. (dI=0.5Cdv/dt)
>
> To achieve a dV of < 0.1V this implies a target impedance of around
20mohm, flat up to 1GHz! (Z=dv/di)
>
> This then seems to need around 500-800 decouping caps spread around,
which is an order of magnitude more than I've ever used in the past.
This is the first time I have taken a 'design' approach to the problem,
but the previous boards have worked, using various rules of thumb.
>
> Is this sort of number of caps to be expected in this sort of system,
or can anyone see any sillies in my understanding (or even in the
sums!)?
>
> Now, if I don't get right out to 1GHz, the edges will suffer, but
that wouldn't necessarily matter if they stayed below 1-1.5ns. Or
would this cause the supply to droop elsewhere?
>
> As you might gather from the analysis above I've read Larry Smith and
co's paper on decoupling design, which states that a flat target
impedance is indicated. If I can analyse my application enough, can I
then shape the Ztarget vs frequency to make life easier?
>
> Many thanks for your time, any help greatly appreciated,
>
> Martin
>
>
>
> TRW Automotive Advanced Product Development,
> Stratford Road, Solihull, B90 4GW. UK
> Tel: +44 (0)121-627-3569
> mailto:martin.j.thompson@trw.com
>
>
>
> **** To unsubscribe from si-list or si-list-digest: send e-mail to
> majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE
> si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
> si-list archives are accessible at http://www.qsl.net/wb6tpu
> ****
>

**** To unsubscribe from si-list or si-list-digest: send e-mail to
majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE
si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu
****


About this list Date view Thread view Subject view Author view

This archive was generated by hypermail 2b29 : Wed Nov 22 2000 - 10:51:02 PST