From: Zabinski, Patrick J. ([email protected])
Date: Tue Aug 15 2000 - 10:19:39 PDT
More or less, yes.
If you look at just the final push-pull transistors
of an output driver, for example, you can take
a stab at the associated dI as:
dI = VDD /
where VDD is supply voltage
Rout = buffer's output impedance (which approximates
the transistor's On resistance)
Zline = characteristic impedance of the line
However, life is not that simple. With the dI, there
will be some voltage drop:
dV = L * dI/dt
So, the equation above looks more like (forgive my
crude use of math):
dI = (VDD - L*dI/dT)/(Rout + Zline)
Not exactly correct, but it should give you an
idea that dI will be decreased from the 'ideal'
Similarly, with lower effective-VDD, dt will slow down
as well, further 'limiting' the problem.
If you look at an extreme case, let's say you had a
2.5V VDD, 8 50 ohm output impedance drivers,
50 ohm impedance lines, 400 psec edge rates,
and 5 nH packaging inductance on the power leads.
The voltage drop by the simple dV = L * dI/dt
formula would be
dV = 5e-9 * (8*2.5/(50 + 50))/400e-12
= 2.5 V.
Before this would happen, the transistors would be
'starved' and the resulting dI would be reduced,
and the resulting dV would be reduced as well.
That said, I still believe the original approach
and theory Martin was following is sound; I just feel
further, non-linear analysis would be useful in
> > * most (all?) dI/dt effects are self-limiting.
> Pat, could you please explain this. I interpret this as: any
> voltage drop/bounce (on power or ground) will cause the I/O
> to slow down
> which will decrease the drop/bounce. Is this what you meant?
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