RE: [SI-LIST] : Decoupling capacitors (again!)

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From: Matt Kaufmann (matt@silicon-spice.com)
Date: Tue Aug 15 2000 - 09:47:51 PDT


> * most (all?) dI/dt effects are self-limiting.

Pat, could you please explain this. I interpret this as: any inductive
voltage drop/bounce (on power or ground) will cause the I/O to slow down
which will decrease the drop/bounce. Is this what you meant?

-Matt

> -----Original Message-----
> From: owner-si-list@silab.eng.sun.com
> [mailto:owner-si-list@silab.eng.sun.com]On Behalf Of Zabinski, Patrick
> J.
> Sent: Tuesday, August 15, 2000 8:41 AM
> To: si-list@silab.eng.sun.com
> Subject: RE: [SI-LIST] : Decoupling capacitors (again!)
>
>
>
> Martin,
>
> I can't offer much advice, but I can possibly offer some
> comfort in that I've had the same problem. For one design
> I was recently involved in, I tried to follow the same
> approach/theory, and the end result was that I needed
> 80 decoupling capacitors per ASIC (to maintain 10%
> dV), and I had 32 ASICs per board (>2500 caps per board!).
> After having others verify
> my numbers/calculations, I took close look and realized
> the caps would consume more board space than the ASICs.
>
> I could not justify, believe, or afford this, so I
> ended up backing down and relying on my old rules of
> thumb (BTW: I hate rules of thumb, but I sometimes
> use them when I have no better way). The board works
> fine with only 12 caps per ASIC.
>
> Looking back, I can see three possible reasons why the approach you
> and I took is not quite complete:
>
> * component packaging effects are not taken to
> account. Not definite on this, but I believe
> a poor package would probably negate any capacitance
> you might have on the board.
> * the board's self-impedance. I believe Larry's
> approach addresses this as effective increase
> in inductance, but the ground/power plane itself
> does offer a low-impedance capacitance. Regardless
> if you have any discrete caps on or not, the planes
> offer some inherent, built-in capacitance.
> * most (all?) dI/dt effects are self-limiting.
> For the calculations you used, they assumed
> dV=0.0. However, if dV>0, then dI/dt will
> be reduced all on its own. I don't have any
> data or theories on how much, but dI/dt
> is likely to be reduced from what you
> predicted (also tied into/related to the
> first issue about packaging).
>
> Sound reasonable? Comments?
>
> Anyway, I sympathize and hope you find a solution. If you
> do, please share.
>
> Pat
>
>
> > -----Original Message-----
> > From: Martin J Thompson [mailto:Martin.J.Thompson@trw.com]
> > Sent: Tuesday, August 15, 2000 9:49 AM
> > To: <"si-list@silab.eng.sun.com"
> > Subject: [SI-LIST] : Decoupling capacitors (again!)
> >
> >
> > Hi all, this is my first time posting here, although I've
> > been lurking for a while.
> >
> > My problem is figuring out the decoupling requirements for
> > this system:
> > FPGA, DSP, 6 SDRAMS, 2 flash, DPRAM, clock frequency is 100MHz.
> >
> > According to my calculations, my I/O's need to drive a total
> > of about 1.5nF of I/O and trace capacitance.
> > To achieve the 0.5ns edges that the FPGA will drive (3.3V
> > supply) it looks like I need dI=4amps. This is assuming that
> > 50% (is this typical?) of the I/O's toggle each cycle. (dI=0.5Cdv/dt)
> >
> > To achieve a dV of < 0.1V this implies a target impedance of
> > around 20mohm, flat up to 1GHz! (Z=dv/di)
> >
> > This then seems to need around 500-800 decouping caps spread
> > around, which is an order of magnitude more than I've ever
> > used in the past. This is the first time I have taken a
> > 'design' approach to the problem, but the previous boards
> > have worked, using various rules of thumb.
> >
> > Is this sort of number of caps to be expected in this sort of
> > system, or can anyone see any sillies in my understanding (or
> > even in the sums!)?
> >
> > Now, if I don't get right out to 1GHz, the edges will suffer,
> > but that wouldn't necessarily matter if they stayed below
> > 1-1.5ns. Or would this cause the supply to droop elsewhere?
> >
> > As you might gather from the analysis above I've read Larry
> > Smith and co's paper on decoupling design, which states that
> > a flat target impedance is indicated. If I can analyse my
> > application enough, can I then shape the Ztarget vs frequency
> > to make life easier?
> >
> > Many thanks for your time, any help greatly appreciated,
> >
> > Martin
> >
> >
> >
> > TRW Automotive Advanced Product Development,
> > Stratford Road, Solihull, B90 4GW. UK
> > Tel: +44 (0)121-627-3569
> > mailto:martin.j.thompson@trw.com
> >
> >
> >
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