From: Martin J Thompson (Martin.J.Thompson@trw.com)
Date: Tue Aug 15 2000 - 07:49:08 PDT
Hi all, this is my first time posting here, although I've been lurking for a while.
My problem is figuring out the decoupling requirements for this system:
FPGA, DSP, 6 SDRAMS, 2 flash, DPRAM, clock frequency is 100MHz.
According to my calculations, my I/O's need to drive a total of about 1.5nF of I/O and trace capacitance.
To achieve the 0.5ns edges that the FPGA will drive (3.3V supply) it looks like I need dI=4amps. This is assuming that 50% (is this typical?) of the I/O's toggle each cycle. (dI=0.5Cdv/dt)
To achieve a dV of < 0.1V this implies a target impedance of around 20mohm, flat up to 1GHz! (Z=dv/di)
This then seems to need around 500-800 decouping caps spread around, which is an order of magnitude more than I've ever used in the past. This is the first time I have taken a 'design' approach to the problem, but the previous boards have worked, using various rules of thumb.
Is this sort of number of caps to be expected in this sort of system, or can anyone see any sillies in my understanding (or even in the sums!)?
Now, if I don't get right out to 1GHz, the edges will suffer, but that wouldn't necessarily matter if they stayed below 1-1.5ns. Or would this cause the supply to droop elsewhere?
As you might gather from the analysis above I've read Larry Smith and co's paper on decoupling design, which states that a flat target impedance is indicated. If I can analyse my application enough, can I then shape the Ztarget vs frequency to make life easier?
Many thanks for your time, any help greatly appreciated,
TRW Automotive Advanced Product Development,
Stratford Road, Solihull, B90 4GW. UK
Tel: +44 (0)121-627-3569
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