RE: [SI-LIST] : Clock routing width/impedance

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From: Matthew Humphreys (humps@sgi.com)
Date: Wed Feb 28 2001 - 10:05:41 PST


Changing the width of the trace won't effect crosstalk. Crosstalk is either
capacitive, (traces running over top of each other) or inductive. (traces
running side by side) To eliminate these, control the edge to edge
separation of the traces, the farther the better, and route adjacent signal
planes orthogonally. Also, limiting the height the signal plane is above
the power plane will help limit inductive crosstalk.

Matt

-----Original Message-----
From: Suchitha.V@smartm.com [mailto:Suchitha.V@smartm.com]
Sent: Wednesday, February 28, 2001 9:00 PM
To: si-list@silab.eng.sun.com
Subject: [SI-LIST] : Clock routing width/impedance

Hello All,

I have a basic question on the selection of width for clock traces for the
purpose of reducing crosstalk.
What should be the ideal width of the clock trace and the impedance of the
trace?
Practically clock widths of 10 mil have been used to reduce the impedance
and hence crosstalk.
Can clock widths of 5 mil be used taking care of the spacing between
serpentines?
In such a case, what are the parameters to be looked into?

Looking forward to your replies and suggestions.

Regards
Suchitha

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