[SI-LIST] : Power/ground bounce on-chip

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From: Lionel COURAU (lionel.courau@st.com)
Date: Fri Jan 26 2001 - 00:45:35 PST


I have a question related to the power/ground bounce generated by the
simultaneous IO switching and the core in deep submicron technology.

The main point i studied last months was the voltage drop generated
by the package inductance of the pins and their mutual capacitances.
As we had quite good package models, we were able to perform accurate
In these conditions, placing power and ground pins close to each other is
an efficient way to reduce the voltage drops in most of cases.

On the other hand, i talked recently to an EMC-concerned design engineer
who think the return current loop inside the chip may generate more
noise than the package inductances.
Therefore he would preferably place power and ground pins distributed
through the whole IO ring (alternately place the same number of power and
ground pins far from each other)so the return current loop should be
statistically minimized.

Did you already made some comparisons between both noise sources,
ie the package inductances and the current loops?
Which effect is the noisiest one?

Please excuse me for my poor english, and thanks in advance for
your help.

Best regards

Library Development Engineer
850, Rue Jean Monnet

E-Mail : lionel.courau@st.comsi-list

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