From: Larry Smith (firstname.lastname@example.org)
Date: Fri Jan 26 2001 - 09:32:47 PST
Lionel - For the core logic power supply, the most important issue is
chip-package resonance. The package has inductance and there is
usually a lot of capacitance between Vdd and Gnd on chip. This forms a
parallel LC tank circuit with a resonant frequency. The circuits on
chip look out into the power supply and see a high impedance at this
frequency, f0 = 1/(2pi*sqrt(LC)). In my experience, that frequency has
been between 20MHz and 100MHz for the last 15 years. Chip capacitance
keeps going up and package inductance keeps going down which keeps the
product of LC relatively constant.
The Q of the circuit is omega*L/R. The most important thing for you to
do is minimize Q by minimizing inductance. You minimize inductance by
placing Vdd next to Gnd and get them as close together as you possibly
can. For an area array, put Vdd and Gnd in a checker board pattern,
alternating Vdd and Gnd. It is possible to get your equivalent
inductance down to the 10's of pH using this technique. This is
required for modern uP's that draw 10's of amps at about 1 volt and
have extremely fast transient rise times.
> Date: Fri, 26 Jan 2001 09:45:35 +0100
> From: Lionel COURAU <email@example.com>
> X-Accept-Language: en
> MIME-Version: 1.0
> To: firstname.lastname@example.org
> Subject: [SI-LIST] : Power/ground bounce on-chip
> Content-Transfer-Encoding: 7bit
> I have a question related to the power/ground bounce generated by the
> simultaneous IO switching and the core in deep submicron technology.
> The main point i studied last months was the voltage drop generated
> by the package inductance of the pins and their mutual capacitances.
> As we had quite good package models, we were able to perform accurate
> In these conditions, placing power and ground pins close to each other is
> an efficient way to reduce the voltage drops in most of cases.
> On the other hand, i talked recently to an EMC-concerned design engineer
> who think the return current loop inside the chip may generate more
> noise than the package inductances.
> Therefore he would preferably place power and ground pins distributed
> through the whole IO ring (alternately place the same number of power and
> ground pins far from each other)so the return current loop should be
> statistically minimized.
> Did you already made some comparisons between both noise sources,
> ie the package inductances and the current loops?
> Which effect is the noisiest one?
> Please excuse me for my poor english, and thanks in advance for
> your help.
> Best regards
> Lionel COURAU
> Library Development Engineer
> 850, Rue Jean Monnet
> F-38926 CROLLES CEDEX
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