RE: [SI-LIST] : RF Via Advice?

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From: Loyer, Jeff W (jeff.w.loyer@intel.com)
Date: Mon Nov 27 2000 - 10:01:32 PST


For what it's worth, we've been doing it for some time without problems.
According to my manufacturing guru, the problem of barrel cracking
dissipated several years ago.

The place where we have gotten into trouble trying to reduce capacitance of
vias had nothing to do with manufacturing. We increased the clearance
around our vias and, inadvertently, through-hole pins. This lead to having
a ground void where a through-hole connector was. Traces routed through the
pins had (predictably) impedance discontinuities. The error wasn't visible
unless the actual gerber files were examined.

Jeff Loyer
(253) 371-8093

-----Original Message-----
From: Bradley S Henson [mailto:bhenson@west.raytheon.com]
Sent: Monday, November 27, 2000 6:52 AM
To: si-list@silab.eng.sun.com
Subject: [SI-LIST] : RF Via Advice?

SI and Board Experts:

I've asked our route folks to use "RF vias" for our 1Gbs fibre channel
signals in our PWBs, where we must use vias. My definition of RF vias, from
the literature, is that the pad is omitted from the signal via on power and
ground layers to reduce capacitance. I also asked for larger than normal
clearances to the planes, assuming no signals routing through the area. The
product design folks have responded by saying there could be a reliability
problem (thermal cycling induced barrel cracking) if they omit the pads
from the internal power and ground layers on my FC signal vias. I'm only
proposing a couple of RF vias in a PWB with 1000's of conventional vias.
Could these few vias really cause a problem? Anyone have any experience
with this? BTW, our boards are typically 14 layer dual offset stripline and
use 4 mil polyimide dielectric layers (fairly lossey, but useable for short
runs). I don't know the via aspect ratio...I'm trying to find out.

Thanks,
Brad Henson, Raytheon

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