# RE: [SI-LIST] : Plane Splits Inspection

From: abe riazi ([email protected])
Date: Thu Nov 09 2000 - 11:46:20 PST

Steve:

Use of three different capacitor values (related by factor of 10x), having different self resonant frequencies, should provide the necessary bandwidth for effective EMI/EMC control, even at sub-nanosecond edge rates.

Regards,

Abe

-----Original Message-----
From: sweir [SMTP:[email protected]]
Sent: Wednesday, November 08, 2000 10:06 PM
To: abe riazi
Subject: RE: [SI-LIST] : Plane Splits Inspection

Abe,

An interesting post. I assume that the first goal is simply not to cross
plane cuts. Stitching capacitors are a distant second best, and even when
SI is adequate may still result in much higher EMI than not crossing a
plane cut.

As far as the multiple cap values are concerned, I disagree with the value
spread. I think that we are only concerned with spectra around the rise /
fall times of the signals, which would not be significantly beyond 10:1. I
think the struggle is to limit the series impedance introduced by the
diversion path through the capacitors to get past the split. For the five
signal suggestion, with 50 ohm synchronous signals, we would need to stay
below 1 ohm for a 10% effective rise in impedance. Given a mounted
inductance in the range of 1.5 - 2nH, this limits us to rise times of no
faster than about 1 - 1.5nS. I think only the 1000pF caps are of any help
here.

Regards,

Steve.
At 06:26 PM 11/8/00 -0800, you wrote:
>A section of my previous email had been deleted. The missing part is
>pasted below:
>
>Certain rules of thumb have been formulated for determination of the
>required number and values of stiching capacitors; an example follows:
>
>For every five traces which cross a plane slot, insert approximately one
>or more capacitors within each 0.250 in. 0.01uF is an acceptable
>value for "stiching" capacitors, though it is preferable to mix several
>different values (i.e. 0.001uF, 0.01uF, 0.1uF) to maximize the bandwidth.
>
>Critical lines such as clock signals can have special requirements and
>However, in a high density PCB it may prove difficult to exactly follow
>such rules when space constraints allow room for fewer capacitors.
>
>The example of Figure 1 has focused only on voids associated with plane
>slots, but the copper voids due to anti-pads of vias and component through
>hole pins can also present adverse effects and require examination.
>
>Regarding differential signals, the best case is of course when none of
>the traces cross the split, and the worst situation can arise when
>only one of the pair runs over the void
>
>To summarize, it is important to inspect a PCB database for plane
>discontinuities before released for fabrication, for at least two reasons:
>
>1. When a high speed-signal crosses a split (or voids) of an adjacent
>plane layer a sudden change can occur in the signal AC return current path
>and trace impedance, accompanied by undesirable SI and EMI effects.
>2. Many EDA simulation tools are incapable of accurately evaluating
>effects of splits on the inductive return current path.
>
>Such visual examination involves superimposing a signal layer, a
>neighboring power (or ground) reference plane and a layer which shows the
>stiching capacitors (usually the top or bottom Silkscreen layer). The
>width of the gaps should be as small as manufacture-able .
>When it is unavoidable for a high-speed net to cross plane
>discontinuities, the routing should be orthogonal (with respect to the
>axis of the slot) to minimize the segment length over the gap.
>
>A final note, I have been informed by Dr. Lynne Green that in a recent
>PADS user conference it has been requested to add the capability of
>highlighting high speed nets which cross plane boundaries. Indeed, this
>would be a desirable feature for a routing or a simulation program!
>
>
>Respectfully,
>
>Abe Riazi
>ServerWorks
>2251 Lawson Lane
>Santa Clara, CA 95054
>
>
>
>
>-----Original Message-----
>From: abe riazi [SMTP:[email protected]]
>Sent: Wednesday, November 08, 2000 5:53 PM
>To: '[email protected]'
>Subject: [SI-LIST] : Plane Splits Inspection
>
> << File: figure1.gif >>
>Dear Scholars:
>
>It is well known that when a high-speed signal crosses a slot of an
>adjacent reference Ground or Power plane, several undesirable effects can
>occur. For instance, a disturbance of return current path takes place
>which can cause a glitch, increased crosstalk and EMI radiation. The rule
>that routing of high-speed nets over voids or cuts of neighboring plane
>layers must be avoided is firmly established in the SI literature. Yet,
>the complexity of modern high speed designs imposes many violations of
>above guideline.
>
>To make matters more complicated, many simulation programs assume
>continuous Ground and Power planes and do not accurately take into account
>effects of plane discontinuities on the return current path. It is
>therefore, important to visually inspect a PCB database for the signals
>crossing plane slots (and voids), before generating the Gerber files and
>releasing the design for fabrication.
>
>Figure 1 illustrates several concepts associated with such examination. A
>section of a power plane is shown having gap G (due to presence of
>multiple powers) and several traces (T1, T2, T3 and T4) of an adjacent
>signal layer which are routed over the splits. C1 and C2 represent two
>stiching capacitors. In this example the gap width is 20 mils. Smaller
>widths (such as 10 mils) can be preferable since the break should be as
>narrow as feasible. Majority of crossings occurs at 90 degree angle with
>respect to axes of slot in order to minimize the segment length over the
>void. Some of the traces contain serpentines but are routed to pass
>boundaries only once. Stiching capacitors are utilized to minimize
>undesirable effects of the cuts.
>
>Certain rules of thumb have been formulated for determination of the
>required number and values of stiching capacitors; an example follows:
>
>For every five traces which cross a plane slot, insert approximately one
>or more capacitors within each 0.250 in. 0.01uF is an acceptable
>value for "stiching" capacitors, though it is preferable to mix several
>2251 Lawson Lane
>Santa Clara, CA 95054
>
>
>
>
>
>
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