[SI-LIST] : Plane Splits Inspection

About this list Date view Thread view Subject view Author view

From: abe riazi (ariazi@serverworks.com)
Date: Wed Nov 08 2000 - 17:53:13 PST

Dear Scholars:

It is well known that when a high-speed signal crosses a slot of an adjacent reference Ground or Power plane, several undesirable effects can occur. For instance, a disturbance of return current path takes place which can cause a glitch, increased crosstalk and EMI radiation. The rule that routing of high-speed nets over voids or cuts of neighboring plane layers must be avoided is firmly established in the SI literature. Yet, the complexity of modern high speed designs imposes many violations of above guideline.

To make matters more complicated, many simulation programs assume continuous Ground and Power planes and do not accurately take into account effects of plane discontinuities on the return current path. It is therefore, important to visually inspect a PCB database for the signals crossing plane slots (and voids), before generating the Gerber files and releasing the design for fabrication.

Figure 1 illustrates several concepts associated with such examination. A section of a power plane is shown having gap G (due to presence of multiple powers) and several traces (T1, T2, T3 and T4) of an adjacent signal layer which are routed over the splits. C1 and C2 represent two stiching capacitors. In this example the gap width is 20 mils. Smaller widths (such as 10 mils) can be preferable since the break should be as narrow as feasible. Majority of crossings occurs at 90 degree angle with respect to axes of slot in order to minimize the segment length over the void. Some of the traces contain serpentines but are routed to pass boundaries only once. Stiching capacitors are utilized to minimize undesirable effects of the cuts.

Certain rules of thumb have been formulated for determination of the required number and values of stiching capacitors; an example follows:

For every five traces which cross a plane slot, insert approximately one or more capacitors within each 0.250 in. 0.01uF is an acceptable value for "stiching" capacitors, though it is preferable to mix several 2251 Lawson Lane
Santa Clara, CA 95054



**** To unsubscribe from si-list or si-list-digest: send e-mail to
majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE
si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu

About this list Date view Thread view Subject view Author view

This archive was generated by hypermail 2b29 : Tue May 08 2001 - 14:30:00 PDT