RE: [SI-LIST] : Parallel single-ended traces routed to achieve 35 Ohm controlledimpedance

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From: Ken Cantrell (Ken.Cantrell@srccomp.com)
Date: Tue Oct 31 2000 - 13:37:50 PST


Salvador,
Yes, I was quick to assume, my apologies. But you have to admit, this is a
strange one, and on the surface it looks like an accident waiting to happen.
One would think that there would be a better, more controlled way to do it
since you are doing a board turn anyway. One of the obvious problems you
will have is modulated Zo going from 70 to 35. Your acceptance function
will only be 0.5, so you will only see a little over half the voltage at the
receiver. Paralleling two TL's isn't like paralleling two resistors. All
you will add with your stitching the two lines together is more ringing from
the via inductance, more crosstalk from the mutual inductance, and a slight
increase in Zo. The impedence seen by either separate drivers or a single
driver driving the two lines will be 70 ohms. However terminating both
lines with a single 35 ohm to ground at the receiver input will achieve the
impedence you desire. Whether or not this will work (just a 35 ohm
shunt)will depend on the number and type of loads you are driving and your
driver characteristics. For example, you may not be able to source that
much current with the present driver, and may need to go to an AC
termination scheme, or you might have to switch to a stronger driver, or you
might have to do both. If you are doing an engineering look see, this
should get you there, but I wouldn't recommend it for a manufactured
product.
Ken

-----Original Message-----
From: owner-si-list@silab.eng.sun.com
[mailto:owner-si-list@silab.eng.sun.com]On Behalf Of
Salvador_Aguinaga@3com.com
Sent: Tuesday, October 31, 2000 11:26 AM
To: Ken Cantrell
Cc: si-list@silab.eng.sun.com
Subject: RE: [SI-LIST] : Parallel single-ended traces routed to achieve
35 Ohm controlledimpedance

Hello Ken,

We have developed clock-driver circuit that benefits from low impedance
lines.
We have tested it in our older system and works well. We decided to add a
test
trace to our new backplane and test the circuit on the new system down the
line.
The backplane's primary design constraints (no. of layers, dielectric
material &
thickness, trace geometry, etc.) were dictated by other application
requirements
and performance objectives. So, now we want to fit this trace (if possible)
and
our board house is recommending we run two 70 Ohm traces in parallel. I
just
want to make sure we do this right --once.

You are incorrect in quickly assuming there was not enough upfront design to
do
this right. Remember that every time you design a PCB one places priority
on
different parts or aspects of your design and normally other constraints
come
into play (over-all thickness, SI of other more important nets, pcb cost,
fabrication issues, etc., etc.). You know where I'm going with this....

All I ask for is: Would some one like to share their knowledge (and results)
in
regards to routing a 70 ohm trace on one set of layers and another of the
same
type on a different set of layers so tha when connected at the ends (and in
between at even intervals) so that their parrallel impedance is 35 Ohms?

Picture this (SIDE VIEW):
_________________________________________ GND Layer
                                           dielectric material
  +=========+=========+===========+ <-----Signal layer 70 ohm impdance
trace
  | | | |
  | | | | dielectric material
_ | _______ | _______ | _________ | _____ GND Layer
  | | | |
  +=========+=========+===========+ <-----Signal layer 70 ohm impdance
trace
   \
    vias dielectric material
_________________________________________ GND Layer

"Ken Cantrell" <Ken.Cantrell@srccomp.com> on 10/31/2000 10:18:06 AM

Sent by: "Ken Cantrell" <Ken.Cantrell@srccomp.com>

To: Salvador Aguinaga/MW/US/3Com, "Michael Nudelman"
<mnudelman@tellium.com>
cc: si-list@silab.eng.sun.com
Subject: RE: [SI-LIST] : Parallel single-ended traces routed to achieve 35
Ohm
      controlledimpedance

Sounds like the cart is before the horse. I would ask why 35 ohms in the
first place. Then if that is a valid requirement, you need to design your
stack up so that you will get 35 ohms across all layers of the board. If
other signals require a Zo of 70 ohms, and these particular traces require
35 ohms, it sounds like there was not enough upfront design going on during
layout. Going back to the drawing board may be the fastest way to resolve
your problem.
-----Original Message-----
From: owner-si-list@silab.eng.sun.com
[mailto:owner-si-list@silab.eng.sun.com]On Behalf Of
Salvador_Aguinaga@3com.com
Sent: Friday, October 27, 2000 2:28 PM
To: Michael Nudelman
Cc: si-list@silab.eng.sun.com
Subject: Re: [SI-LIST] : Parallel single-ended traces routed to achieve
35 Ohm controlledimpedance

I need to run the trace through the a pin field. The room between pins is
2mm
and because of the dielectric thickness constraint I can only run a single
12
mil wide line through the pin field. If I use a single 35 ohm line, the
trace
width is too large to fit through the pin field.

Thanks,
-- Sal

Michael Nudelman <mnudelman@tellium.com> on 10/27/2000 03:10:31 PM

Sent by: Michael Nudelman <mnudelman@tellium.com>

To: Salvador Aguinaga/MW/US/3Com
cc: si-list@silab.eng.sun.com
Subject: Re: [SI-LIST] : Parallel single-ended traces routed to achieve 35
Ohm
      controlledimpedance

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