From: [email protected]
Date: Tue Oct 31 2000 - 10:26:23 PST
Hello Ken,
We have developed clock-driver circuit that benefits from low impedance lines.
We have tested it in our older system and works well. We decided to add a test
trace to our new backplane and test the circuit on the new system down the line.
The backplane's primary design constraints (no. of layers, dielectric material &
thickness, trace geometry, etc.) were dictated by other application requirements
and performance objectives. So, now we want to fit this trace (if possible) and
our board house is recommending we run two 70 Ohm traces in parallel. I just
want to make sure we do this right --once.
You are incorrect in quickly assuming there was not enough upfront design to do
this right. Remember that every time you design a PCB one places priority on
different parts or aspects of your design and normally other constraints come
into play (over-all thickness, SI of other more important nets, pcb cost,
fabrication issues, etc., etc.). You know where I'm going with this....
All I ask for is: Would some one like to share their knowledge (and results) in
regards to routing a 70 ohm trace on one set of layers and another of the same
type on a different set of layers so tha when connected at the ends (and in
between at even intervals) so that their parrallel impedance is 35 Ohms?
Picture this (SIDE VIEW):
_________________________________________ GND Layer
dielectric material
+=========+=========+===========+ <-----Signal layer 70 ohm impdance trace
| | | |
| | | | dielectric material
_ | _______ | _______ | _________ | _____ GND Layer
| | | |
+=========+=========+===========+ <-----Signal layer 70 ohm impdance trace
\
vias dielectric material
_________________________________________ GND Layer
"Ken Cantrell" <[email protected]> on 10/31/2000 10:18:06 AM
Sent by: "Ken Cantrell" <[email protected]>
To: Salvador Aguinaga/MW/US/3Com, "Michael Nudelman" <[email protected]>
cc: [email protected]
Subject: RE: [SI-LIST] : Parallel single-ended traces routed to achieve 35 Ohm
controlledimpedance
Sounds like the cart is before the horse. I would ask why 35 ohms in the
first place. Then if that is a valid requirement, you need to design your
stack up so that you will get 35 ohms across all layers of the board. If
other signals require a Zo of 70 ohms, and these particular traces require
35 ohms, it sounds like there was not enough upfront design going on during
layout. Going back to the drawing board may be the fastest way to resolve
your problem.
-----Original Message-----
From: [email protected]
[mailto:[email protected]]On Behalf Of
[email protected]
Sent: Friday, October 27, 2000 2:28 PM
To: Michael Nudelman
Cc: [email protected]
Subject: Re: [SI-LIST] : Parallel single-ended traces routed to achieve
35 Ohm controlledimpedance
I need to run the trace through the a pin field. The room between pins is
2mm
and because of the dielectric thickness constraint I can only run a single
12
mil wide line through the pin field. If I use a single 35 ohm line, the
trace
width is too large to fit through the pin field.
Thanks,
-- Sal
Michael Nudelman <[email protected]> on 10/27/2000 03:10:31 PM
Sent by: Michael Nudelman <[email protected]>
To: Salvador Aguinaga/MW/US/3Com
cc: [email protected]
Subject: Re: [SI-LIST] : Parallel single-ended traces routed to achieve 35
Ohm
controlledimpedance
**** To unsubscribe from si-list or si-list-digest: send e-mail to
[email protected]. In the BODY of message put: UNSUBSCRIBE
si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu
****
This archive was generated by hypermail 2b29 : Tue May 08 2001 - 14:29:54 PDT