Re: [SI-LIST] : Electrical Analysis to prove the soundness of a design

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From: Michael Nudelman (mnudelman@tellium.com)
Date: Fri Oct 27 2000 - 06:32:08 PDT


John Lin:

As for questions 2 and 3 (timing/skew), well - besides the point, that
you know your layout and always can accurately predict added timing/skew
dur to the traces, the rest is all in the datasheets - I prefer to use
worst case numbers, of course.

Mike.

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