From: Lynne Green ([email protected])
Date: Tue Aug 29 2000 - 11:08:45 PDT
RE: [SI-LIST] : hold time dilemmaJim-
Tco includes some of the flight time in the buffer delay, so just adding
pin-to-pin flight time does some double-counting. Check out our
Technical Application note on timing correction:
http://www.hyperlynx.com/appnotes.htm
Also, watch out if signal crosses VIH or VIL more than once, since
this affects min/max flight time.
- Lynne
-----Original Message-----
From: [email protected]
[mailto:[email protected]]On Behalf Of Beal, Weston
Sent: Tuesday, August 29, 2000 10:23 AM
To: '[email protected]'
Subject: RE: [SI-LIST] : hold time dilemma
Jim,
Not to fear (too much). The equation that you need is
Tco(min) + Tflight(min) - skew > Thold
First of all, get good models of your clock inputs and simulate and specify
correctly your clock traces in order to minmize skew. Then make your memory
bus just long enough to make Tflight(min) add enough time delay to get past
the Thold. Now make sure that you didn't break the setup time :)
Regards,
Weston
+ -----Original Message-----
+ From: Peterson, James F (FL51) [mailto:[email protected]]
+ Sent: Tuesday, August 29, 2000 10:00 AM
+ To: [email protected]
+ Subject: [SI-LIST] : hold time dilemma
+
+
+ Here's my hold time dilemma/question :
+
+ I have a synchronous ram with a tco (clk to valid out) of
+ (1ns,3ns). I have
+ a processor with a tHold of 1ns (min). Taking the min. tco
+ for a hold time
+ analysis gives me 0ns of margin. Any clock skew at all
+ between the ram and
+ the processor makes this fail timing analysis.
+
+ It used to be that one solution was to invert the clock to
+ the ram, but
+ these days it's hard to justify cutting the board's settling
+ time by 50% (At
+ 100MHz, you've gone from a starting budget of 10ns to one of 5ns).
+
+ What are some you high speed board designers doing about this?
+
+ (BTW : This reminds me of a story : about 6 years ago I purchased a
+ computer. I noticed that the machine locked up every once in
+ a while. At
+ first I thought it was the typical OS problems we all
+ encounter, but it was
+ occurring so frequently I called the supplier. They responded
+ that my case
+ was a known problem with that mother board and the fix was to
+ go into the
+ bios and disable the external synchronous L2 cache!!!!)
+
+ best regards,
+
+ Jim
+
+ > Jim Peterson
+ > [email protected]
+ > Honeywell Space Systems
+ > M/S 934-5
+ > 13350 U.S. Hwy 19 N.
+ > Clearwater FL, 33764-7290
+ > Office : 727-539-2719
+ > Fax : 727-539-2183
+ >
+
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