[SI-LIST] : Jitter generation and tolerance in high freq. circuits

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From: ramesh srinivasan (ramesh.srinivasan@wipro.com)
Date: Fri Jul 14 2000 - 01:44:39 PDT


Hi All,
I would like to have some opinion regarding jitter generation and
tolerance of devices
which work at high optical frequencies extending to 2.4 Gbps.
I would ,in particular, like to know about jitter generation in clock
and data recovery devices.
Most of the device datasheets I have seen give incomplete info about
jitter generations.
First of all, they give jitter values for recovered clock and data, with
the assumption that there is
no jitter on the input data stream. Secondly, they donot give any jitter
transfer characteristics.

I would like to know if any one has any experience with boards having
clock and data recovery units.
In my design, I am assuming that a jitter on the input data to a CDR,
will give output jitters (the value
of which is specified by the device datasheets) that would be identical
on the clock and data streams,
since the clock is recovered from the data.
If my assumption is correct, I can design with equal length traces for
the recovered data and clock,
and avoid timing violations.

1. Am I right in assuming that identical phase jitters appear on the
outputs ??
2. Also, are there any other impacts of jitter besides causing timing
violations ??
3. Can I assume the clock to Data delay of transceivers to be inclusive
of worst case jitters ??

Regards and Thanks
Ramesh Srinivasan
VLSI System Design Engineer
Wipro Global R & D
email : ramesh.srinivasan@wipro.com

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