RE: [SI-LIST] : Power Plane Inductance

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From: Chris Cheng (chris.cheng@3pardata.com)
Date: Thu Jul 13 2000 - 15:19:32 PDT


back to the same argument i have a while ago.
"it is useless to try to bypass high speed noise in pcb"
as a matter of fact u have ignored two important inductance
path before the die noise hit the pcb
(i) the cranshaft core via in a flip chip package
(ii) the excess inductance on the pwr/gnd perforated plane
near the i/o escape vias area on the package
both are very stubtle and large inductance that people
usually ignore.
do it on die or on top of the package
chris

-----Original Message-----
From: Larry Smith [mailto:Larry.Smith@Eng.Sun.COM]
Sent: Thursday, July 13, 2000 9:06 AM
To: si-list@silab.eng.sun.com
Subject: Re: [SI-LIST] : Power Plane Inductance

Brian - I assume that your power is carried on power and ground planes
in your 4 layer pcb stackup. You mention a 62 mil thick board. Boards
of this nature usually have a stackup with sig1/power/gnd/sig2. To
achieve trace impedance's for the signal lines near 50 ohms, the
dielectric layer between signals and return planes are usually 3 to 7
mils. That leaves nearly 50 mils separation between the power and
ground planes in order to get to a 62 mil total thickness.

The spreading inductance for power planes is directly proportional to
the dielectric thickness. Typical numbers are as follows:

        dielectric spreading
        thickness inductance
        ----------- ----------
         2 mils 65 pH/square
         4 130
         8 260
        16 520
        50 mils 1.625 nH/square!

Units in 'inductance/square' are interpreted similar to spreading
resistance in ohms/square. Count the number of curvilinear squares in
series and in parallel between the source and sink and you can find the
inductance. Use the pitch between power and ground vias at the
decoupling capacitor and BGA pattern as the diameters of the source and
sink. From a single cap to a single BGA power/ground pair, there is
usually about 1 equivalent square after all the parallel and series
combinations have been worked out.

But if you have 10 decoupling capacitors mounted on power planes
servicing 10 pairs of power/ground on your BGA, you will quickly find
that the path between a single BGA pair and a single capacitor is
nearly 10 squares long or 16nH for your board! If you have done a good
job with capacitor mounting pads, vias and BGA ball definition, the
mounting inductance for the components is approximately 1 nH.

By far, the dominant inductance in your system is the pcb power
planes. The most effective way to reduce that inductance is to use
power planes that are spaced closely together. We use adjacent power
planes that are spaced 4 mils or 2 mils apart in our high speed, high
reliability systems. We are supporting materials vendors who are
providing power plane cores with dielectric thicknesses of 1 mil or
less. We think this is vitally important to achieve low impedance
power at hundreds of MHz, going to the GHz region.

regards,
Larry Smith
Sun Microsystems

> From: "Moran, Brian P" <brian.p.moran@intel.com>
> To: si-list@silab.eng.sun.com
> Cc: "Moran, Brian P" <brian.p.moran@intel.com>
> Subject: [SI-LIST] : Power Plane Inductance
> Date: Wed, 12 Jul 2000 14:19:45 -0700
> MIME-Version: 1.0
>
> Hi All,
>
> I am trying to do some back of the envelope power delivery analysis, and I
> need a number for inductance from a BGA package pad pin escape, to a
> decoupling capacitor, located 0.5' to 1.0" from the via site. Can anyone
> throw out a good guess, or quote existing data, for power and ground path
> inductance from BGA pad to decoupling capacitor pad, for a typical 4 layer
> 62 mil thick PCB, using 1 oz power planes, with a 50 mil pitch BGA, using
> interstitial pin escapes with a 15 mil wide trace, and 25/40 thermals,
with
> 4-8mil spokes. I'm not asking someone to field solve for me, I was just
> hoping someone had used similiar geometries in the past, or had some good
> rules of thumb they might share. I have data for various configurations of
> capacitor pad/via configurations, but nothing for the rest of the path.
>
> Brian Moran
> Signal Integrity Engineer
> Intel Corporation
> Folsom, CA
>

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