RE: [SI-LIST] : wire bond vs flip chip?

About this list Date view Thread view Subject view Author view

From: Volk, Andrew M (andrew.m.volk@intel.com)
Date: Wed Jun 14 2000 - 08:52:06 PDT


If you include bond wire length and package trace lengths together, the
total should be about the same for the same number of I/O signals. The
electrical characteristics will be much better for signals and especially
power delivery based on bond wire inductance alone. My signaling
assumptions are based on a package with a ground plane. We have multilayer
packages that also allow stripline routing. But comparing 4-layer BGA
packaging, flip-chip is much better electrically than wire bond.

Andrew Volk
Intel Corp.

-----Original Message-----
From: Perry Qu [mailto:perry.qu@alcatel.com]
Sent: Wednesday, June 14, 2000 6:53 AM
To: si-list@silab.eng.sun.com
Subject: Re: [SI-LIST] : wire bond vs flip chip?

Hi! Chuang:

IMHO, flip-chip packaging need not to be full matrix. You can use
depopulated matrix as well. In such situation, electrical performance
should be better than the wire-bond version.

The problem with full matrix pattern is that you may have difficulty in
routing at the packaging substrate level and you may need more routing
layers. For those pins at the center, you have to punch a via and lead
the signal to another layer to route. I think you can still achieve good
electrical performance through proper design, such as placing grounding
vias besides your signals, etc. Maybe those designers working with
microprocessor packaging can give us a better picture.

Just my 2 cents.

-- 
Perry Qu

EMI/Signal Integrity Specialist, EMC Engineering Alcatel CID

600 March Road Kanata, ON K2K 2E6 Canada

DID: (613) 7846720 FAX: (613) 5993642 Email: perry.qu@alcatel.com

Weber Chuang wrote: > > Dear SI-listers, > > We had an internal discussion about the next generation packaging of our > chip, and flip-chip is intuitively to have less inductance because there is > no wire bond, but one of our people says that because our chip is high pin > count chip, so the traces on substrate connecting I/O pads and balls will > become extra long since flip chip will have I/O pads in a matrix style, > while wire bond BGA uses only the outer ring for on die pads allocation, so > not much benefit could be gained on electrical performance, do you agree on > this of do you have any experience or thought that you could share with me? > Thanks in advance for your help and enlightenment. > > Best Regards > Weber Chuang( e) > Signal & Timing Integrity Engineer, > VIA Technologies, Inc. Taipei, Taiwan, ROC > TEL : 886-2-22185452 ext : 6522 > mailto:weber@via.com.tw > http://www.via.com.tw > Very Innovative Architecture > > **** To unsubscribe from si-list or si-list-digest: send e-mail to > majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE > si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP. > si-list archives are accessible at http://www.qsl.net/wb6tpu > ****

**** To unsubscribe from si-list or si-list-digest: send e-mail to majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu ****

**** To unsubscribe from si-list or si-list-digest: send e-mail to majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu ****


About this list Date view Thread view Subject view Author view

This archive was generated by hypermail 2b29 : Wed Nov 22 2000 - 10:50:37 PST