From: Weber Chuang (WeberChuang@via.com.tw)
Date: Wed Jun 14 2000 - 02:17:56 PDT
We had an internal discussion about the next generation packaging of our
chip, and flip-chip is intuitively to have less inductance because there is
no wire bond, but one of our people says that because our chip is high pin
count chip, so the traces on substrate connecting I/O pads and balls will
become extra long since flip chip will have I/O pads in a matrix style,
while wire bond BGA uses only the outer ring for on die pads allocation, so
not much benefit could be gained on electrical performance, do you agree on
this of do you have any experience or thought that you could share with me?
Thanks in advance for your help and enlightenment.
Weber Chuang( ²ø´º²e)
Signal & Timing Integrity Engineer,
VIA Technologies, Inc. Taipei, Taiwan, ROC
TEL : 886-2-22185452 ext : 6522
Very Innovative Architecture
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