Re: [SI-LIST] : Re: [SI-LIST] Bypassing of large fpga's

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From: cadpro2k@dacafe.com
Date: Fri Jun 02 2000 - 12:45:35 PDT


Bill,

I'll second what Barry said, and add, most any bypassing scheme lends
itself to using buried capacitive layers. If you were to just add the
capacitive layers to your existing "power" planes, which may or may not
be in close proximity to the "ground" planes, you'd enjoy the added
capacitance value and probably some decrease in noise.

References will be provided if required.

Mitch

---------Included Message----------
> Date: 2 Jun 2000 10:22:40 -0700
> From: "Barry Ma" <barry_ma@altavista.com>
> Reply-To: "Barry Ma" <barry_ma@altavista.com>
> To: <mcgiffb@ttc.com>
> Cc: <si-list@silab.eng.sun.com>
> Subject: [SI-LIST] : Re: [SI-LIST] Bypassing of large fpga's
>
> Bill,
>
> I cannot understand what you said: "Thought about buried
capacitance, but our
> power plane scheme doesn't lend itself to that." ... I don't
think it's a good
> idea to separate the pwr and gnd planes. ...
>
> Regards,
> Barry Ma
> bma@ANRITSU.com
>
>
>
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