[SI-LIST] : RE: Split Plane

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From: Barry Ma (barry_ma@altavista.com)
Date: Mon May 22 2000 - 10:14:28 PDT


Dean,

Actually in Brad's case, there's no need to stitch up the gap between 3.3V and 5V areas because no signal trace would use this pwr plane for return plane. Sorry, it was Friday evening when I was in a hurry to reply Brad's Email.

Generally speaking, many EMC design engineers stitch the gap between different pwr areas on the same pwr plane with capacitors, allowing RF return signal to flow across the gap. …The value and interval of those caps depends on the frequency of the RF signal.

Regards,
Barry Ma
bma@ANRITSU.com
------------
On Mon, 22 May 2000, Dean Gonzales wrote:

> Hi Barry,
>
> I am particularly interested in your comment about 'stitching' the gap... Can you recommend how this will be best performed and/or share some common rules of thumb you find effective. To keep cost low I have had to hack several planes for multiple power supplies. In doing so we were able to make sure all signals are dual-referenced symmetric striplines, but I have not taken any measure to stitch.
>
> Thanks in advance for your advice.
>
> Regards,
>
> Dean.
>
> -----Original Message-----
> From: Barry Ma [SMTP:barry_ma@altavista.com]
> Sent: Friday, May 19, 2000 5:27 PM
> To: crowell@amirix.com
> Cc: si-list@silab.eng.sun.com
> Subject: re: Split Plane
>
> Brad,
>
> Here is my two cents worth:
> Did you consider exchanging 7 and 8 for more capacitance between 5V and gnd planes? Suppose you have 10 mil or less plane spacing. I understand that you want to use a gnd plane as return plane for signals on layer 9. But it's OK to use 3.3V plane as return plane. The plane cap would work well to let return signals go from 3.3V plane back to gnd pins on layer 9.
>
> It's also OK using part of 5V plane as additional 3V area. You'd better stitch up the gap.
>
> Regards,
> Barry Ma
> bma@ANRITSU.com
> -------------
> From: "Brad Crowell" <crowell@amirix.com>, on 5/19/00 2:04 PM:
>
> I have been lurking in the shadows of the SI list for some time now, but
> have come across a situation that I could use some advice on:
>
> I am working on a board design that is using the following stackup:
>
> 1 - SIGNAL
> 2 - GROUND
> 3 - SIGNAL
> 4 - SIGNAL
> 5 - GROUND
> 6 - 5V PLANE
> 7 - 3.3V PLANE
> 8 - GROUND
> 9 - SIGNAL
> 10- SIGNAL
> 11- GROUND
> 12- SIGNAL
>
> My problem is that we are running out of routing resources. Thus,
> it has been suggested that a few traces could be routed on layer 6,
> the 5v plane. The intent would be to route some traces for the 3.3v
> devices which are located away from the 5v devices on the board. This
> would reduce the effect of any splits in the plane. Also, since there
> is a ground plane available as a reference for every signal layer,
> a split in a supply plane shouldn't have much effect, if any. I am
> inclined to think, with my limited SI experience, that this should
> be ok, but would appreciate comments from some of the experts.

>
>
> Thanks,
> Brad

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