Re: [SI-LIST] : On chip decoupling

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From: D. C. Sessions (dcs@lumbercartel.com)
Date: Fri May 25 2001 - 07:48:02 PDT


On Thursday 24 May 2001 13:38, Tom Zimmerman wrote:
> Hi,
>
> I don't know if this fits into any of the categories typically discussed
> here, but I need a little advice from any on-chip decoupling experts out
> there. If anybody has any expertise in this area, I'd welcome any comments.
>
> Is on chip decoupling common? How is it typically done? Nwell to
> substrate? Thinox to Nwell? How is the Q of the circuit limited? How much
> decoupling capacitance can one safely put on a chip? How are reliability
> concerns addressed?

On-chip decoupling is pretty much essential for any realistic chip. Do the
L*di/dt calculation for nontrivial clock systems and practical bondwire
inductances and you'll see why.

That said, a lot of chips with large amounts of random logic get by with the
energy storage on quiescent gates. The nightmare scenario only comes up
when the supply currents are fairly coherent, as for instance in a highly
pipelined design.

Far and away the most effective capacitance is gate oxide capacitors. Anything
else has too much ESR to be useful. Long-channel P and N devices (not too
long or the ESR bug bites) both work fine; just tie the P gate to Vss and the source
and drain to Vdd (and vice versa for N). You do need good supply ESD protection,
but anything between the gates and the rails ruins the high-frequency performance.

> I am designing a mixed signal chip in the TSMC .25u process which contains a
> large analog pipeline with lots of channels and sample capacitors, and I
> would like to bypass the analog VDD on chip. Here is the approach I have
> taken:
>
> Since there is lots of "free space" under the array of sample caps on the
> chip, I have implemented lots (12000) of series RC circuits which all
> connect between analog VDD and substrate (analog ground). Each C is about
> 1pF and consists of a 40/4 PMOS transistor gate (thinox) in an Nwell. The
> Nwell is connected directly to VDD, and the PMOS gate goes through an 8K
> poly resistor to analog ground. Thus the equivalent circuit for all 12000
> of these is about 0.012 uF in series with a 0.66 ohm resistor. I put the
> resistors in for 2 reasons: 1) Lower the Q to limit the ringing, 2)
> Improve the yield, since if any one capacitor has a short, the current is
> limited to an insignificant value by an 8K resistor. Tens of capacitors
> could actually be shorted on the chip without affecting the bypassing or
> current draw significantly.

I think you're excessively concerned with gate failures. Our yield data
convinced us that this wasn't a big issue. Talk to your process people.

> This scheme takes a lot of space, but on this chip the space is free anyway.
> Is this a reasonable approach? Is there a better method? Any advice would
> be greatly appreciated!

Sometimes when circumstances allow we build N-channel devices in an N-well
to get better isolation and reduce the threshold voltage (which also helps the ESR.)

-- 
| I'm old enough that I don't have to pretend to be grown up.|
+----------- D. C. Sessions <dcs@lumbercartel.com> ----------+

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