Re: [SI-LIST] : On chip decoupling

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From: Tom Zimmerman (zimmerman@fnal.gov)
Date: Fri May 25 2001 - 08:19:46 PDT


----- Original Message -----
From: "D. C. Sessions" <dcs@lumbercartel.com>
To: <si-list@silab.eng.sun.com>
Sent: Friday, May 25, 2001 9:48 AM
Subject: Re: [SI-LIST] : On chip decoupling

> Far and away the most effective capacitance is gate oxide capacitors.
Anything
> else has too much ESR to be useful. Long-channel P and N devices (not too
> long or the ESR bug bites) both work fine; just tie the P gate to Vss and
the source
> and drain to Vdd (and vice versa for N). You do need good supply ESD
protection,
> but anything between the gates and the rails ruins the high-frequency
performance.
>

I'm not sure what you mean by "between the gates and the rails." Which
gates? Could you clarify?

Also, how do you limit the Q to avoid ringing on the supply? Does the
inherent resistance of the long channel device accomplish this?

Thanks much for your comments!

Tom Z.

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