[SI-LIST] : On chip decoupling

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From: Tom Zimmerman (zimmerman@fnal.gov)
Date: Thu May 24 2001 - 13:38:00 PDT


Hi,

I don't know if this fits into any of the categories typically discussed
here, but I need a little advice from any on-chip decoupling experts out
there. If anybody has any expertise in this area, I'd welcome any comments.

Is on chip decoupling common? How is it typically done? Nwell to
substrate? Thinox to Nwell? How is the Q of the circuit limited? How much
decoupling capacitance can one safely put on a chip? How are reliability
concerns addressed?

I am designing a mixed signal chip in the TSMC .25u process which contains a
large analog pipeline with lots of channels and sample capacitors, and I
would like to bypass the analog VDD on chip. Here is the approach I have
taken:

Since there is lots of "free space" under the array of sample caps on the
chip, I have implemented lots (12000) of series RC circuits which all
connect between analog VDD and substrate (analog ground). Each C is about
1pF and consists of a 40/4 PMOS transistor gate (thinox) in an Nwell. The
Nwell is connected directly to VDD, and the PMOS gate goes through an 8K
poly resistor to analog ground. Thus the equivalent circuit for all 12000
of these is about 0.012 uF in series with a 0.66 ohm resistor. I put the
resistors in for 2 reasons: 1) Lower the Q to limit the ringing, 2)
Improve the yield, since if any one capacitor has a short, the current is
limited to an insignificant value by an 8K resistor. Tens of capacitors
could actually be shorted on the chip without affecting the bypassing or
current draw significantly.

This scheme takes a lot of space, but on this chip the space is free anyway.
Is this a reasonable approach? Is there a better method? Any advice would
be greatly appreciated!

Tom Zimmerman
Fermilab
zimmerman@fnal.gov

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