From: Zabinski, Patrick J. ([email protected])
Date: Tue Aug 08 2000 - 12:24:43 PDT
We've seen thieving implemented in an array of dots to large
planes to a complex series of open lines, each of which have
had some effect on SI (not sure about EMC).
The dots are generally the least of concern due to their
small size. The worst situation we've seen is where the dots
are located close enough to traces and/or components to effectively
add parasitic capacitance (e.g., reduce the impedance of a line).
The planes are generally pretty good assuming two things: 1)
they are far enough away from lines to not couple to or load
critical traces; and 2) the are properly tied down to ground or
power to not become a resonant structure (i.e., read about
microstrip patch antennas if you'd like to see what an
improper plane can do).
The splattering of traces is the worst in that you cannot tie
each and every one of them down (to avoid resonance), and signals
seem to couple to them regardless of how far away they are.
All that said, more and more PCB vendors are relying strictly
on the dots for thieving, and it hasn't been too big of an
issue for us when applied to the outer layers.
One point problem we did find is when we had a plane on
one side of an internal layer and striplines on the other.
The vendor added thieving dots around the striplines, which
created large effectiving loading caps for the striplines on the
Probably not a solid reference you're hoping for, but hopefully
gives you some generalities to be paying attention to.
> -----Original Message-----
> From: Greim, Michael [mailto:[email protected]]
> Sent: Tuesday, August 08, 2000 1:04 PM
> To: SI LIST
> Cc: 'mgreim'
> Subject: [SI-LIST] : Effects of thieving on SI and EMC.....
> Does anyone out there have a tool or reference
> that would allow one to calculate the effects of
> thieving patterns on signal integrity and EMC.
> I am trying to come up with appropriate rule sets
> for driving an auto-thiever utility.
> Thanks for the help.
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