[SI-LIST] : Non-Montonicity at Pin vs. Die

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From: gregory.heiler@kodak.com
Date: Tue Feb 27 2001 - 09:12:36 PST


From: Gregory N Heiler

Hello All,

We have been looking at a simulation of a clock driver driving highly
inductive inputs and are seeing non-monotonic falling edges at the pin but
at the die it looks ok. The non-monotonicty is approximately 0.6v in
amplitude and occurs at 1.5v for about 0.5 ns. It seems that since the
waveform looks clean at the die the waveform at the pin shouldn't matter.
However, with the tolerances and inaccuracies I am wondering if the
prudent thing to do is to clean up the pin waveform. Would you pass a
design with this behavior?

The high inductance is approximately 12nH and this is the pin inductance of
the Tape BGA Package. The inputs drive PLL's so I am very concerned about
the non-montonicities. It's a series terminated point to point net and
changing the series termination has little impact on the non-monotonicity
We are simulating with IBIS Models and the ICX IS Tool.

If this has been discussed and is in the archive a mention of that would be
appreciated.

Thanks for Any Sharing of Insight in Advance.

Regards;

Greg

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