From: D. C. Sessions (firstname.lastname@example.org)
Date: Tue Feb 27 2001 - 20:16:49 PST
On Tuesday 27 February 2001 10:12, email@example.com wrote:
# From: Gregory N Heiler
# Hello All,
# We have been looking at a simulation of a clock driver driving highly
# inductive inputs and are seeing non-monotonic falling edges at the pin but
# at the die it looks ok. The non-monotonicty is approximately 0.6v in
# amplitude and occurs at 1.5v for about 0.5 ns. It seems that since the
# waveform looks clean at the die the waveform at the pin shouldn't matter.
# However, with the tolerances and inaccuracies I am wondering if the
# prudent thing to do is to clean up the pin waveform. Would you pass a
# design with this behavior?
# The high inductance is approximately 12nH and this is the pin inductance of
# the Tape BGA Package. The inputs drive PLL's so I am very concerned about
# the non-montonicities. It's a series terminated point to point net and
# changing the series termination has little impact on the non-monotonicity
# We are simulating with IBIS Models and the ICX IS Tool.
# If this has been discussed and is in the archive a mention of that would be
I'm a bit confused on your context, so bear with me.
If you're referring to a clock DRIVER, nobody cares what the die waveform
looks like, what matters is the waveform at the receiver(s) down the line,
which are in turn more closely related to the pin waveform.
If you're referring to a clock RECEIVER, then the die waveform is indeed
critical, and a slope reversal at 1.5 v is nasty regardless. Even a shelf
in the switching region tends to greatly increase your timing uncertainty.
On the other hand, I suspect that you're modeling the package as a
lumped inductance which is far from reality. Before freaking out, try doing
a better job of modeling the package.
-- | I'm old enough that I don't have to pretend to be grown up.| +----------- D. C. Sessions <firstname.lastname@example.org> ----------+
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