[SI-LIST] : PECL known problem

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From: Mikhail Matusov (matusov@squarepeg.ca)
Date: Mon Feb 26 2001 - 12:03:46 PST


Hi all,

I was wondering if someone could help me. I have a production mixed
digital/RF board with main clock distributed as PECL. Recently after
upgrading our software we discovered that we are having problem with phase
stability of our RF signal during the times of an external CPU activity. The
problem was tracked down to the clock and it became clear that we are
dealing with a classic case of PECL sensitivity to changes in VCC line. The
clock goes up and down, rising time is not infinite, so it translates into
timing shifts... I tried changing termination schemes to decrease rise time
but unfortunately this brings in EMI problems and it does not seem to fully
solve the original problem either...

The clock is about 50MHz. There is a provision for the series at source
termination and for the RC termination (2 resistors with common capacitor)
at the end.

Any ideas?

============================
Mikhail Matusov
Hardware Design Engineer
Square Peg Communications
Tel.: 1 (613) 271-0044 ext.231
Fax: 1 (613) 271-3007
http://www.squarepeg.ca

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