RE: [SI-LIST] : questions concerning a E-PBGA

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From: Jennifer Pencis (jpencis@innoveda.com)
Date: Fri Feb 02 2001 - 06:30:20 PST


 BGA routing tools are available from Pads today. The tool is called
PowerBGA. It does a good job of automating the process. It can even import
other CAD tools die geometries and set up land patterns, etc. You may want
to get an eval.

-----Original Message-----
From: jan.vercammen.jv1@belgium.agfa.com
To: si-list@silab.eng.sun.com
Sent: 2/2/01 5:25 AM
Subject: [SI-LIST] : questions concerning a E-PBGA

hello SI_list,

I have some questions concerning an enhanced plastic ball grid array
(E-PBGA).

We are using a Motorola MPC107, a PowerPC chipset bridge. It uses an
E-PBGA as
package (I think?). The chip has a 2.5V core voltage and a
3.3V I/O voltage. The chip itself is flip-chip mounted (its back is up).

If I look at the package thru a microscoop then I can see at least 3
layers with
conductors:
-1- the top layer (L1) carries or seems to carry most signal conductors.
I
estimate the line width at about 70-80micron. The signal tracks
      end in pads for the solder balls.
-2- the first inner layer (L2) seems to carry some kind of mesh, a
spider-like
web that fans out to the perimeter of the substrate. The mesh does not
seem
      to be connected to any of the solder balls. I have also found
signal
tracks in layer 2 that connect to solder ball pads. These seem not to be
      part of the mesh.
-3- the next layer (L3) is almost solid, with the exception at the
solder ball
positions and a large number of circular holes. I cannot find any
      connections to solder balls.
-4- at the substrate perimeter there is a ring in the top layer and
possibly the
2nd layer, it seems to be connected to some signals or power supply.
-5- I cannot see more layers, though I assume that there is at least one
more.

My questions (hints, suggestions are welcome):
-a- is this a 4-layer or higher layer substrate?
-b- what is the material used for PBGA and E-PBGAs? An idea of the
permitivity?
Common track widths?
-c- what is the mesh for in the 2nd layer L2?
-d- need the layer buildup be symmetric, as in PCBs?
-e- where can I find design rules for these kind of packages? Any
on-line??
-f- similar as -e-, who makes layout tools for these kind of packaging?

Thank you for your help.

Regards,

Jan Vercammen
EMC/PCB Engineering Agfa-Gevaert NV

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