From: D. C. Sessions ([email protected])
Date: Tue Jan 23 2001 - 06:51:45 PST
On Monday 22 January 2001 08:40, Yehuda D. Yizraeli wrote:
# Looking for a rule of thumb for the number of power pads for a chip running
# 135Mhz, 32Bits, driving at slopes of 1nSec to 3.3V 25pf.
I don't see why you'd hang a 25 pf capacitor on the pin :-)
OK, the rule that I use goes like this:
Calculate your timing margin w/o regard to SSO pushout.
Using an IBIS model, determine the slow-case drive into your line impedance.
Translate this into an equivalent resistance (e.g., 3.0 volts/30 mA = 100 ohms)
Determine your equivalent supply inductance per pin. Take mutual inductance
into account only if you have a reliable model for it.
N = Tmargin*R/(2*Lpin)
So if you have 1400 ps of margin, a 100 ohm slow-case drive/line combo,
and 7 nH per supply pin you get 10:1:1 signal:power:ground, which is probably
higher than you would want to use for other reasons.
-- | I'm old enough that I don't have to pretend to be grown up.| +----------- D. C. Sessions <[email protected]> ----------+
**** To unsubscribe from si-list or si-list-digest: send e-mail to [email protected] In the BODY of message put: UNSUBSCRIBE si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu ****
This archive was generated by hypermail 2b29 : Tue May 08 2001 - 14:30:43 PDT