Date: Tue Dec 12 2000 - 09:35:11 PST
Actually you can increase the board thickness and still have it fit into
the backplane. Remember, you're only increasing one side of the board...
Your connector mating plane won't change. What you do is increase the
side opposite the backplane connector (say increase it to .093"
thckness, and then mill back (on the card guide sides) to .063" on that
side you increased. We've done that in many instances. It will work.
Have a mechanical guy model it up for you. :)
As for what Mike Geim mentioned, do have the Cadence guy look into the
conjestion issues, and verify he needs all the routing layers. If you're
using a "high pin count BGA" it might be necessary, but I wouldn't say I
always know for a fact how many layers I need prior to routing. Taking a
few day to verify this might be worth it. And, ALWAYS verify with your
fabrication house that they can meet your minimum requirements. Often
times you might find they can do better than what you're after, and that
could give you even more latitude. :)
Best of times...
Sr PCB Designer
San Diego, CA
(Mike, I think you could also offer an apology to your remark about us
PCB Designers not wanting to listen to ideas to make our jobs easier.
Your company might employ some narrow minded designers, but that's not
the case with many of the designers I know. I'll be watching.)
> Date: Tue, 12 Dec 2000 17:57:18 +0200
> From: "Aric Hadav" <Aric@accord.co.il>
> Reply-To: "Aric Hadav" <Aric@accord.co.il>
> To: "'e'" <email@example.com>
> Cc: "'firstname.lastname@example.org'" <email@example.com>
> Subject: RE: [SI-LIST] : layer stackup
> the board is connected to a backplane,so if you increase the
> the board connectors won't connect to the backplane connectors.
> hence - I thought off trimming/cutting the board to 1.6 mm in
this side as
> well, but doing so
> will destroy the connectors pads.
> that's why I cannot change the alignment of the board compared to
> I'll be happy to receive any more ideas on the matter.
> -----Original Message-----
> From: e [mailto:firstname.lastname@example.org]
> Sent: Tuesday, December 12, 2000 5:36 PM
> To: Aric Hadav
> Cc: 'email@example.com'; 'Dave Hoover'
> Subject: Re: [SI-LIST] : layer stackup
> Is it possible to add more layers to the board, and so increase
> but keep it at 1.6 mm along the edges where it must be inserted
> Aric Hadav wrote:
> > Hi,
> > board thickness is fixed to 1.6 mm because of card guides.
> > I thought of making a wider card and cutting it at the edges to
1.6 mm but
> > that makes too many problems, hence I'm staying with 1.6mm.
> > regarding the board warpage, the layout guy told me the layout
> > Cadence)
> > has a copper balance feature that insures a balanced board by
the end of
> > layout.
> > still, I'm not confident with that.
> > has anyone has a better stackup in 1.6 mm ? or other ideas ?
> > thanks,
> > Aric
> > -----Original Message-----
> > From: Dave Hoover [mailto:firstname.lastname@example.org]
> > Sent: Tuesday, December 12, 2000 4:08 AM
> > To: Aric Hadav; 'email@example.com'
> > Subject: Re: [SI-LIST] : layer stackup
> > Aric,
> > 14 layers in 1.6 mm is tough but possible. It looks
> > like your forced to go this way based on necessary
> > signal layers. Unfortunately this stackup you've
> > proposed is not well balanced. There may be a
> > considerate amount of warpage because of this
> > unbalanced stackup. Being 1.6mm thk just compounds
> > the warpage. Is there any way to add redundant
> > planes (to balance the stackup) and increase the
> > overall thickness? (Is the thickness locked in due
> > to card guides, pressfit pin lengths, or something?)
> > Dave Hoover (fab guy learning about SI)
> > --- Aric Hadav <Aric@accord.co.il> wrote:
> > > Hi,
> > >
> > > I'm looking for some help on deciding on my board
> > > layer stackup.
> > > my design has ~20K pads and it must fit into a
> > > standard 6U board, 1.6 mm
> > > thick.
> > > the board thickness CAN NOT be changed.
> > >
> > > the PCB layout guy told me that the design can only
> > > fit into a minimum of 14
> > > layers stack up,
> > > with a 3-4 mil core and preg thickness, as described
> > > below:
> > > 1. CS
> > > 2. sig1
> > > 3. VCC1V8
> > > 4. sig2
> > > 5. sig3 (ctrl impedance).
> > > 6. sig4
> > > 7. GND
> > > 8. sig5
> > > 9. sig6 (ctrl impedance).
> > > 10. sig7
> > > 11. VCC3V
> > > 12. sig8
> > > 13. sig9
> > > 14. PS
> > >
> > > now, this looks some what strange to me since layers
> > > 5 & 9 aren't adjacent
> > > to a PWR/GND
> > > plane, since one should always try that a signal
> > > layer will be close to
> > > reference plane.
> > > now, in order to reduce the crosstalk between layers
> > > 4 to 6 or 8 to 10 he
> > > suggested to route the
> > > signals not horizontally and vertically but
> > > layers 4, 8 - 45 degrees.
> > > layers 5, 9 - vertical or horizontal.
> > > layers 6, 10 - 135 degrees.
> > > has anyone routed this way ? did it work ok ?
> > > the signal clocks will be routed in layers 5 and 9
> > > which supposed to be
> > > control impedance. is it ok ?
> > > has anyone has other suggestions to the layer
> > > stuckup?
> > >
> > > thanks,
> > >
> > > Aric Hadav
> > > Hardware Design Engineer
> > > firstname.lastname@example.org
> > >
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